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[147.11.224.80]) by smtp.gmail.com with ESMTPSA id b19sm7292575pft.74.2020.06.08.07.18.28 (version=TLS1 cipher=AES128-SHA bits=128/128); Mon, 08 Jun 2020 07:18:28 -0700 (PDT) From: Bin Meng To: Alistair Francis , Bastian Koppelmann , Palmer Dabbelt , Sagar Karandikar , qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH 11/15] hw/riscv: sifive_u: Add a new property msel for MSEL pin state Date: Mon, 8 Jun 2020 07:17:40 -0700 Message-Id: <1591625864-31494-12-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1591625864-31494-1-git-send-email-bmeng.cn@gmail.com> References: <1591625864-31494-1-git-send-email-bmeng.cn@gmail.com> Received-SPF: pass client-ip=2607:f8b0:4864:20::1041; envelope-from=bmeng.cn@gmail.com; helo=mail-pj1-x1041.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bin Meng Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Bin Meng On SiFive FU540 SoC, the value stored at physical address 0x1000 stores the MSEL pin state that is used to control the next boot location that ROM codes jump to. Add a new property msel to sifive_u machine for this. Signed-off-by: Bin Meng Reviewed-by: Alistair Francis --- hw/riscv/sifive_u.c | 7 +++++++ include/hw/riscv/sifive_u.h | 1 + 2 files changed, 8 insertions(+) diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index 07e2ba0..aaa5adb 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -507,6 +507,13 @@ static void sifive_u_machine_instance_init(Object *obj) "Set on to tell QEMU's ROM to jump to " "flash. Otherwise QEMU will jump to DRAM"); + s->msel = 0; + object_property_add(obj, "msel", "uint32", + sifive_u_machine_get_uint32_prop, + sifive_u_machine_set_uint32_prop, NULL, &s->msel); + object_property_set_description(obj, "msel", + "Mode Select (MSEL[3:0]) pin state"); + s->serial = OTP_SERIAL; object_property_add(obj, "serial", "uint32", sifive_u_machine_get_uint32_prop, diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h index dcf7f3b..d82cfe0 100644 --- a/include/hw/riscv/sifive_u.h +++ b/include/hw/riscv/sifive_u.h @@ -63,6 +63,7 @@ typedef struct SiFiveUState { int fdt_size; bool start_in_flash; + uint32_t msel; uint32_t serial; } SiFiveUState;