From patchwork Tue Nov 6 07:13:27 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Liu, Jingqi" X-Patchwork-Id: 993524 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=intel.com Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 42q1CF4XrKz9sDn for ; Tue, 6 Nov 2018 18:19:53 +1100 (AEDT) Received: from localhost ([::1]:39368 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gJveR-0000gy-1L for incoming@patchwork.ozlabs.org; Tue, 06 Nov 2018 02:19:51 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:47884) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gJvdf-0000g4-3y for qemu-devel@nongnu.org; Tue, 06 Nov 2018 02:19:04 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gJvdd-0007Cy-28 for qemu-devel@nongnu.org; Tue, 06 Nov 2018 02:19:03 -0500 Received: from mga04.intel.com ([192.55.52.120]:41913) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gJvdc-00070M-Ng for qemu-devel@nongnu.org; Tue, 06 Nov 2018 02:19:01 -0500 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga006.jf.intel.com ([10.7.209.51]) by fmsmga104.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 05 Nov 2018 23:19:00 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.54,470,1534834800"; d="scan'208";a="88904535" Received: from optiplex-7050.sh.intel.com ([10.239.161.26]) by orsmga006.jf.intel.com with ESMTP; 05 Nov 2018 23:18:59 -0800 From: Liu Jingqi To: pbonzini@redhat.com, ehabkost@redhat.com, rth@twiddle.net Date: Tue, 6 Nov 2018 15:13:27 +0800 Message-Id: <1541488407-17045-3-git-send-email-jingqi.liu@intel.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1541488407-17045-1-git-send-email-jingqi.liu@intel.com> References: <1541488407-17045-1-git-send-email-jingqi.liu@intel.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 192.55.52.120 Subject: [Qemu-devel] [PATCH v2 2/2] x86/cpu: Enable MOVDIR64B cpu feature X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Liu Jingqi , tao3.xu@intel.com, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" MOVDIR64B moves 64-bytes as direct-store with 64-bytes write atomicity. Direct store is implemented by using write combining (WC) for writing data directly into memory without caching the data. The bit definition: CPUID.(EAX=7,ECX=0):ECX[bit 28] MOVDIR64B The release document ref below link: https://software.intel.com/sites/default/files/managed/c5/15/\ architecture-instruction-set-extensions-programming-reference.pdf Cc: Xu Tao Signed-off-by: Liu Jingqi --- target/i386/cpu.c | 2 +- target/i386/cpu.h | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index d9ab68c..32e1551 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -1024,7 +1024,7 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = { "la57", NULL, NULL, NULL, NULL, NULL, "rdpid", NULL, NULL, "cldemote", NULL, "movdiri", - NULL, NULL, NULL, NULL, + "movdir64b", NULL, NULL, NULL, }, .cpuid = { .eax = 7, diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 3debba3..937a3a2 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -688,6 +688,7 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS]; #define CPUID_7_0_ECX_RDPID (1U << 22) #define CPUID_7_0_ECX_CLDEMOTE (1U << 25) /* CLDEMOTE Instruction */ #define CPUID_7_0_ECX_MOVDIRI (1U << 27) /* MOVDIRI Instruction */ +#define CPUID_7_0_ECX_MOVDIR64B (1U << 28) /* MOVDIR64B Instruction */ #define CPUID_7_0_EDX_AVX512_4VNNIW (1U << 2) /* AVX512 Neural Network Instructions */ #define CPUID_7_0_EDX_AVX512_4FMAPS (1U << 3) /* AVX512 Multiply Accumulation Single Precision */