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[8/8] sun4u_iommu: add trace event for IOMMU translations

Message ID 1511703326-25325-9-git-send-email-mark.cave-ayland@ilande.co.uk
State New
Headers show
Series sparc: IOMMU tidy-up and reorganisation | expand

Commit Message

Mark Cave-Ayland Nov. 26, 2017, 1:35 p.m. UTC 
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
---
 hw/sparc64/sun4u_iommu.c |    2 ++
 hw/sparc64/trace-events  |    1 +
 2 files changed, 3 insertions(+)

Comments

Philippe Mathieu-Daudé Nov. 26, 2017, 3:18 p.m. UTC | #1 
On 11/26/2017 10:35 AM, Mark Cave-Ayland wrote:
> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

> ---
>  hw/sparc64/sun4u_iommu.c |    2 ++
>  hw/sparc64/trace-events  |    1 +
>  2 files changed, 3 insertions(+)
> 
> diff --git a/hw/sparc64/sun4u_iommu.c b/hw/sparc64/sun4u_iommu.c
> index 51fbc39..4cf8e69 100644
> --- a/hw/sparc64/sun4u_iommu.c
> +++ b/hw/sparc64/sun4u_iommu.c
> @@ -184,6 +184,8 @@ static IOMMUTLBEntry sun4u_translate_iommu(IOMMUMemoryRegion *iommu,
>          ret.addr_mask = (IOMMU_PAGE_SIZE_8K - 1);
>      }
>  
> +    trace_sun4u_iommu_translate(ret.iova, ret.translated_addr, tte);
> +
>      return ret;
>  }
>  
> diff --git a/hw/sparc64/trace-events b/hw/sparc64/trace-events
> index 052352f..2ee2d75 100644
> --- a/hw/sparc64/trace-events
> +++ b/hw/sparc64/trace-events
> @@ -6,3 +6,4 @@ ebus_isa_irq_handler(int n, int level) "Set ISA IRQ %d level %d"
>  # hw/sparc64/sun4u_iommu.c
>  sun4u_iommu_mem_read(uint64_t addr, uint64_t val, int size) "addr: 0x%"PRIx64" val: 0x%"PRIx64" size: %d"
>  sun4u_iommu_mem_write(uint64_t addr, uint64_t val, int size) "addr: 0x%"PRIx64" val: 0x%"PRIx64" size: %d"
> +sun4u_iommu_translate(uint64_t addr, uint64_t trans_addr, uint64_t tte) "xlate 0x%"PRIx64" => pa 0x%"PRIx64" tte: 0x%"PRIx64
>
diff mbox series

Patch

diff --git a/hw/sparc64/sun4u_iommu.c b/hw/sparc64/sun4u_iommu.c
index 51fbc39..4cf8e69 100644
--- a/hw/sparc64/sun4u_iommu.c
+++ b/hw/sparc64/sun4u_iommu.c
@@ -184,6 +184,8 @@  static IOMMUTLBEntry sun4u_translate_iommu(IOMMUMemoryRegion *iommu,
         ret.addr_mask = (IOMMU_PAGE_SIZE_8K - 1);
     }
 
+    trace_sun4u_iommu_translate(ret.iova, ret.translated_addr, tte);
+
     return ret;
 }
 
diff --git a/hw/sparc64/trace-events b/hw/sparc64/trace-events
index 052352f..2ee2d75 100644
--- a/hw/sparc64/trace-events
+++ b/hw/sparc64/trace-events
@@ -6,3 +6,4 @@  ebus_isa_irq_handler(int n, int level) "Set ISA IRQ %d level %d"
 # hw/sparc64/sun4u_iommu.c
 sun4u_iommu_mem_read(uint64_t addr, uint64_t val, int size) "addr: 0x%"PRIx64" val: 0x%"PRIx64" size: %d"
 sun4u_iommu_mem_write(uint64_t addr, uint64_t val, int size) "addr: 0x%"PRIx64" val: 0x%"PRIx64" size: %d"
+sun4u_iommu_translate(uint64_t addr, uint64_t trans_addr, uint64_t tte) "xlate 0x%"PRIx64" => pa 0x%"PRIx64" tte: 0x%"PRIx64