From patchwork Mon Oct 9 21:06:59 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Cave-Ayland X-Patchwork-Id: 823522 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3y9tBc2MB9z9t5Q for ; Tue, 10 Oct 2017 08:08:24 +1100 (AEDT) Received: from localhost ([::1]:59802 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e1fHh-0004I6-TP for incoming@patchwork.ozlabs.org; Mon, 09 Oct 2017 17:08:21 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:56673) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e1fGu-0004Ft-V5 for qemu-devel@nongnu.org; Mon, 09 Oct 2017 17:07:33 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1e1fGt-0006dI-T1 for qemu-devel@nongnu.org; Mon, 09 Oct 2017 17:07:32 -0400 Received: from chuckie.co.uk ([82.165.15.123]:40550 helo=s16892447.onlinehome-server.info) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1e1fGt-0006aY-Lm for qemu-devel@nongnu.org; Mon, 09 Oct 2017 17:07:31 -0400 Received: from host109-153-37-179.range109-153.btcentralplus.com ([109.153.37.179] helo=kentang.home) by s16892447.onlinehome-server.info with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.76) (envelope-from ) id 1e1fGs-0003wf-2y; Mon, 09 Oct 2017 22:07:31 +0100 From: Mark Cave-Ayland To: qemu-devel@nongnu.org, atar4qemu@gmail.com Date: Mon, 9 Oct 2017 22:06:59 +0100 Message-Id: <1507583223-14819-5-git-send-email-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1507583223-14819-1-git-send-email-mark.cave-ayland@ilande.co.uk> References: <1507583223-14819-1-git-send-email-mark.cave-ayland@ilande.co.uk> X-SA-Exim-Connect-IP: 109.153.37.179 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk X-SA-Exim-Version: 4.2.1 (built Sun, 08 Jan 2012 02:45:44 +0000) X-SA-Exim-Scanned: Yes (on s16892447.onlinehome-server.info) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 82.165.15.123 Subject: [Qemu-devel] [PATCH 4/8] sun4m: move DMA device wiring from sparc32_dma_init() to sun4m_hw_init() X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" By using the sysbus interface it is possible to wire up the esp/le devices to the sun4m DMA controller directly during sun4m_hw_init() instead of passing qemu_irqs into the sparc32_dma_init() function. Signed-off-by: Mark Cave-Ayland --- hw/sparc/sun4m.c | 29 ++++++++++++++++------------- 1 file changed, 16 insertions(+), 13 deletions(-) diff --git a/hw/sparc/sun4m.c b/hw/sparc/sun4m.c index 88a9752..4f2ed4b 100644 --- a/hw/sparc/sun4m.c +++ b/hw/sparc/sun4m.c @@ -307,8 +307,7 @@ static void *iommu_init(hwaddr addr, uint32_t version, qemu_irq irq) return s; } -static void *sparc32_dma_init(hwaddr daddr, qemu_irq parent_irq, - void *iommu, qemu_irq *dev_irq, int is_ledma) +static void *sparc32_dma_init(hwaddr daddr, void *iommu, int is_ledma) { DeviceState *dev; SysBusDevice *s; @@ -317,8 +316,6 @@ static void *sparc32_dma_init(hwaddr daddr, qemu_irq parent_irq, qdev_prop_set_ptr(dev, "iommu_opaque", iommu); qdev_init_nofail(dev); s = SYS_BUS_DEVICE(dev); - sysbus_connect_irq(s, 0, parent_irq); - *dev_irq = qdev_get_gpio_in(dev, 0); sysbus_mmio_map(s, 0, daddr); return s; @@ -821,9 +818,10 @@ static void sun4m_hw_init(const struct sun4m_hwdef *hwdef, DeviceState *slavio_intctl; const char *cpu_model = machine->cpu_model; unsigned int i; - void *iommu, *espdma, *ledma, *nvram; - qemu_irq *cpu_irqs[MAX_CPUS], slavio_irq[32], slavio_cpu_irq[MAX_CPUS], - espdma_irq, ledma_irq; + void *iommu, *nvram; + DeviceState *espdma, *ledma; + SysBusDevice *sbd; + qemu_irq *cpu_irqs[MAX_CPUS], slavio_irq[32], slavio_cpu_irq[MAX_CPUS]; qemu_irq esp_reset, dma_enable; qemu_irq fdc_tc; unsigned long kernel_size; @@ -882,11 +880,13 @@ static void sun4m_hw_init(const struct sun4m_hwdef *hwdef, empty_slot_init(hwdef->iommu_pad_base,hwdef->iommu_pad_len); } - espdma = sparc32_dma_init(hwdef->dma_base, slavio_irq[18], - iommu, &espdma_irq, 0); + espdma = sparc32_dma_init(hwdef->dma_base, iommu, 0); + sbd = SYS_BUS_DEVICE(espdma); + sysbus_connect_irq(sbd, 0, slavio_irq[18]); - ledma = sparc32_dma_init(hwdef->dma_base + 16ULL, - slavio_irq[16], iommu, &ledma_irq, 1); + ledma = sparc32_dma_init(hwdef->dma_base + 16ULL, iommu, 1); + sbd = SYS_BUS_DEVICE(ledma); + sysbus_connect_irq(sbd, 0, slavio_irq[16]); if (graphic_depth != 8 && graphic_depth != 24) { error_report("Unsupported depth: %d", graphic_depth); @@ -939,7 +939,8 @@ static void sun4m_hw_init(const struct sun4m_hwdef *hwdef, empty_slot_init(hwdef->sx_base, 0x2000); } - lance_init(&nd_table[0], hwdef->le_base, ledma, ledma_irq); + lance_init(&nd_table[0], hwdef->le_base, ledma, + qdev_get_gpio_in(ledma, 0)); nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0, 0x2000, 1968, 8); @@ -971,7 +972,9 @@ static void sun4m_hw_init(const struct sun4m_hwdef *hwdef, esp_init(hwdef->esp_base, 2, espdma_memory_read, espdma_memory_write, - espdma, espdma_irq, &esp_reset, &dma_enable); + espdma, + qdev_get_gpio_in(espdma, 0), + &esp_reset, &dma_enable); qdev_connect_gpio_out(espdma, 0, esp_reset); qdev_connect_gpio_out(espdma, 1, dma_enable);