From patchwork Fri Jul 7 12:29:30 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Llu=C3=ADs_Vilanova?= X-Patchwork-Id: 785474 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3x3vBK6yNTz9s7B for ; Fri, 7 Jul 2017 22:32:09 +1000 (AEST) Received: from localhost ([::1]:56211 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dTSQZ-0008OJ-Mi for incoming@patchwork.ozlabs.org; Fri, 07 Jul 2017 08:32:07 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39830) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dTSON-0006ot-HS for qemu-devel@nongnu.org; Fri, 07 Jul 2017 08:29:52 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dTSOJ-0000cs-El for qemu-devel@nongnu.org; Fri, 07 Jul 2017 08:29:51 -0400 Received: from roura.ac.upc.edu ([147.83.33.10]:53526 helo=roura.ac.upc.es) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dTSOI-0000cE-UP for qemu-devel@nongnu.org; Fri, 07 Jul 2017 08:29:47 -0400 Received: from correu-1.ac.upc.es (correu-1.ac.upc.es [147.83.30.91]) by roura.ac.upc.es (8.13.8/8.13.8) with ESMTP id v67CTgq7021300; Fri, 7 Jul 2017 14:29:42 +0200 Received: from localhost (63.red-83-51-187.dynamicip.rima-tde.net [83.51.187.63]) by correu-1.ac.upc.es (Postfix) with ESMTPSA id DEDF1258; Fri, 7 Jul 2017 14:29:36 +0200 (CEST) From: =?utf-8?b?TGx1w61z?= Vilanova To: qemu-devel@nongnu.org Date: Fri, 7 Jul 2017 14:29:30 +0200 Message-Id: <149943057043.8972.16059991065061793515.stgit@frigg.lan> X-Mailer: git-send-email 2.13.2 In-Reply-To: <149942760788.8972.474351671751194003.stgit@frigg.lan> References: <149942760788.8972.474351671751194003.stgit@frigg.lan> User-Agent: StGit/0.17.1-dirty MIME-Version: 1.0 X-MIME-Autoconverted: from 8bit to quoted-printable by roura.ac.upc.es id v67CTgq7021300 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6.x [fuzzy] X-Received-From: 147.83.33.10 Subject: [Qemu-devel] [PATCH v12 12/27] target/i386: [tcg] Port to generic translation framework X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Eduardo Habkost , Peter Crosthwaite , "Emilio G. Cota" , Paolo Bonzini , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Richard Henderson Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Lluís Vilanova Reviewed-by: Richard Henderson Reviewed-by: Emilio G. Cota Tested-by: Emilio G. Cota --- target/i386/translate.c | 121 +++++++---------------------------------------- 1 file changed, 19 insertions(+), 102 deletions(-) diff --git a/target/i386/translate.c b/target/i386/translate.c index 94b09e0f6d..22a22aea8d 100644 --- a/target/i386/translate.c +++ b/target/i386/translate.c @@ -8450,6 +8450,10 @@ static void i386_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cpu) cpu_cc_srcT = tcg_temp_local_new(); } +static void i386_tr_tb_start(DisasContextBase *db, CPUState *cpu) +{ +} + static void i386_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu) { DisasContext *dc = container_of(dcbase, DisasContext, base); @@ -8468,7 +8472,7 @@ static BreakpointCheckType i386_tr_breakpoint_check( /* The address covered by the breakpoint must be included in [tb->pc, tb->pc + tb->size) in order to for it to be properly cleared -- thus we increment the PC here so that - the logic setting tb->size below does the right thing. */ + the generic logic setting tb->size later does the right thing. */ dc->base.pc_next += 1; return BC_HIT_TB; } else { @@ -8539,109 +8543,22 @@ static void i386_tr_disas_log(const DisasContextBase *dcbase, } -/* generate intermediate code for basic block 'tb'. */ -void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) -{ - DisasContext dc1, *dc = &dc1; - int num_insns; - int max_insns; - - /* generate intermediate code */ - dc->base.singlestep_enabled = cs->singlestep_enabled; - dc->base.tb = tb; - dc->base.is_jmp = DISAS_NEXT; - dc->base.pc_first = tb->pc; - dc->base.pc_next = dc->base.pc_first; - i386_tr_init_disas_context(&dc->base, cs); - - num_insns = 0; - max_insns = tb->cflags & CF_COUNT_MASK; - if (max_insns == 0) { - max_insns = CF_COUNT_MASK; - } - if (max_insns > TCG_MAX_INSNS) { - max_insns = TCG_MAX_INSNS; - } - - gen_tb_start(tb); - for(;;) { - i386_tr_insn_start(&dc->base, cs); - num_insns++; - - if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) { - CPUBreakpoint *bp; - QTAILQ_FOREACH(bp, &cs->breakpoints, entry) { - if (bp->pc == dc->base.pc_next) { - BreakpointCheckType bp_check = - i386_tr_breakpoint_check(&dc->base, cs, bp); - switch (bp_check) { - case BC_MISS: - /* Target ignored this breakpoint, go to next */ - break; - case BC_HIT_INSN: - /* Hit, keep translating */ - /* - * TODO: if we're never going to have more than one - * BP in a single address, we can simply use a - * bool here. - */ - goto done_breakpoints; - case BC_HIT_TB: - /* Hit, end TB */ - goto done_generating; - default: - g_assert_not_reached(); - } - } - } - } - done_breakpoints: - - if (num_insns == max_insns && (tb->cflags & CF_LAST_IO)) { - gen_io_start(); - } - - dc->base.pc_next = i386_tr_translate_insn(&dc->base, cs); - /* stop translation if indicated */ - if (dc->base.is_jmp) { - break; - } - /* if single step mode, we generate only one instruction and - generate an exception */ - if (dc->base.singlestep_enabled) { - dc->base.is_jmp = DISAS_TOO_MANY; - break; - } - /* if too long translation, stop generation too */ - if (tcg_op_buf_full() || - num_insns >= max_insns) { - dc->base.is_jmp = DISAS_TOO_MANY; - break; - } - if (singlestep) { - dc->base.is_jmp = DISAS_TOO_MANY; - break; - } - } - i386_tr_tb_stop(&dc->base, cs); - if (tb->cflags & CF_LAST_IO) - gen_io_end(); -done_generating: - gen_tb_end(tb, num_insns); +static const TranslatorOps i386_tr_ops = { + .init_disas_context = i386_tr_init_disas_context, + .tb_start = i386_tr_tb_start, + .insn_start = i386_tr_insn_start, + .breakpoint_check = i386_tr_breakpoint_check, + .translate_insn = i386_tr_translate_insn, + .tb_stop = i386_tr_tb_stop, + .disas_log = i386_tr_disas_log, +}; -#ifdef DEBUG_DISAS - if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM) - && qemu_log_in_addr_range(dc->base.pc_first)) { - qemu_log_lock(); - qemu_log("----------------\n"); - i386_tr_disas_log(&dc->base, cs); - qemu_log("\n"); - qemu_log_unlock(); - } -#endif +/* generate intermediate code for basic block 'tb'. */ +void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb) +{ + DisasContext dc; - tb->size = dc->base.pc_next - dc->base.pc_first; - tb->icount = num_insns; + translator_loop(&i386_tr_ops, &dc.base, cpu, tb); } void restore_state_to_opc(CPUX86State *env, TranslationBlock *tb,