From patchwork Wed Jul 5 17:13:34 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?C=C3=A9dric_Le_Goater?= X-Patchwork-Id: 784790 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3x2p2L08mtz9s4s for ; Thu, 6 Jul 2017 03:36:26 +1000 (AEST) Received: from localhost ([::1]:47395 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dSoDv-0006kn-LY for incoming@patchwork.ozlabs.org; Wed, 05 Jul 2017 13:36:23 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:42096) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dSnuO-0004uy-8u for qemu-devel@nongnu.org; Wed, 05 Jul 2017 13:16:13 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dSnuK-0004Dk-8H for qemu-devel@nongnu.org; Wed, 05 Jul 2017 13:16:12 -0400 Received: from 11.mo3.mail-out.ovh.net ([87.98.184.158]:50555) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dSnuK-0004DM-1v for qemu-devel@nongnu.org; Wed, 05 Jul 2017 13:16:08 -0400 Received: from player158.ha.ovh.net (b6.ovh.net [213.186.33.56]) by mo3.mail-out.ovh.net (Postfix) with ESMTP id C76E8FCDC3 for ; Wed, 5 Jul 2017 19:16:06 +0200 (CEST) Received: from zorba.kaod.org.com (LFbn-1-10652-153.w90-89.abo.wanadoo.fr [90.89.238.153]) (Authenticated sender: clg@kaod.org) by player158.ha.ovh.net (Postfix) with ESMTPSA id 9CC4E62007E; Wed, 5 Jul 2017 19:16:00 +0200 (CEST) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: David Gibson Date: Wed, 5 Jul 2017 19:13:34 +0200 Message-Id: <1499274819-15607-22-git-send-email-clg@kaod.org> X-Mailer: git-send-email 2.7.5 In-Reply-To: <1499274819-15607-1-git-send-email-clg@kaod.org> References: <1499274819-15607-1-git-send-email-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 2221963468931173350 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrfeelkedrudeigdduuddtucetufdoteggodetrfdotffvucfrrhhofhhilhgvmecuqfggjfdpvefjgfevmfevgfenuceurghilhhouhhtmecufedttdenucesvcftvggtihhpihgvnhhtshculddquddttddm X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 87.98.184.158 Subject: [Qemu-devel] [RFC PATCH 21/26] ppc/xive: introduce routines to allocate IRQ numbers X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , qemu-ppc@nongnu.org, Alexander Graf , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" The IRQ number allocator is inspired by OPAL which allocates IPI IRQ numbers from the bottom of the IRQ number space and allocates the HW IRQ numbers from the top. So, this might be slightly overkill for our need. Needs to be discussed. Signed-off-by: Cédric Le Goater --- hw/intc/xive.c | 53 +++++++++++++++++++++++++++++++++++++++++++++++++++ include/hw/ppc/xive.h | 1 + 2 files changed, 54 insertions(+) diff --git a/hw/intc/xive.c b/hw/intc/xive.c index bec123649ebd..42eefbe7fd65 100644 --- a/hw/intc/xive.c +++ b/hw/intc/xive.c @@ -748,6 +748,59 @@ void xive_ics_create(XiveICSState *xs, XIVE *x, uint32_t offset, } /* + * IRQ number allocators + */ +uint32_t xive_alloc_hw_irqs(XIVE *x, uint32_t count, uint32_t align) +{ + uint32_t base; + int i; + + base = x->int_hw_bot - count; + base &= ~(align - 1); + if (base < x->int_ipi_top) { + qemu_log_mask(LOG_GUEST_ERROR, + "XIVE: HW alloc request for %d interrupts " + "aligned to %d failed\n", + count, align); + return -1; + } + + x->int_hw_bot = base; + + for (i = 0; i < count; i++) { + XiveIVE *ive = xive_get_ive(x, base + i); + + ive->w = IVE_VALID | IVE_MASKED; + } + return base; +} + +static uint32_t xive_alloc_ipi_irqs(XIVE *x, uint32_t count, uint32_t align) +{ + uint32_t base; + int i; + + base = x->int_ipi_top + (align - 1); + base &= ~(align - 1); + if (base >= x->int_hw_bot) { + qemu_log_mask(LOG_GUEST_ERROR, + "IPI alloc request for %d interrupts aligned to %d " + "failed\n", + count, align); + return -1; + } + + x->int_ipi_top = base + count; + + for (i = 0; i < count; i++) { + XiveIVE *ive = xive_get_ive(x, base + i); + + ive->w = IVE_VALID | IVE_MASKED; + } + return base; +} + +/* * Main XIVE object */ diff --git a/include/hw/ppc/xive.h b/include/hw/ppc/xive.h index a1c7797658ba..3c1cd96ea4d0 100644 --- a/include/hw/ppc/xive.h +++ b/include/hw/ppc/xive.h @@ -69,6 +69,7 @@ void xive_spapr_init(sPAPRMachineState *spapr); void xive_spapr_populate(XIVE *x, void *fdt); void xive_mmio_map(XIVE *x); +uint32_t xive_alloc_hw_irqs(XIVE *x, uint32_t count, uint32_t align); void xive_ics_create(XiveICSState *xs, XIVE *x, uint32_t offset, uint32_t nr_irqs, uint32_t shift, uint32_t flags,