@@ -748,6 +748,59 @@ void xive_ics_create(XiveICSState *xs, XIVE *x, uint32_t offset,
}
/*
+ * IRQ number allocators
+ */
+uint32_t xive_alloc_hw_irqs(XIVE *x, uint32_t count, uint32_t align)
+{
+ uint32_t base;
+ int i;
+
+ base = x->int_hw_bot - count;
+ base &= ~(align - 1);
+ if (base < x->int_ipi_top) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "XIVE: HW alloc request for %d interrupts "
+ "aligned to %d failed\n",
+ count, align);
+ return -1;
+ }
+
+ x->int_hw_bot = base;
+
+ for (i = 0; i < count; i++) {
+ XiveIVE *ive = xive_get_ive(x, base + i);
+
+ ive->w = IVE_VALID | IVE_MASKED;
+ }
+ return base;
+}
+
+static uint32_t xive_alloc_ipi_irqs(XIVE *x, uint32_t count, uint32_t align)
+{
+ uint32_t base;
+ int i;
+
+ base = x->int_ipi_top + (align - 1);
+ base &= ~(align - 1);
+ if (base >= x->int_hw_bot) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "IPI alloc request for %d interrupts aligned to %d "
+ "failed\n",
+ count, align);
+ return -1;
+ }
+
+ x->int_ipi_top = base + count;
+
+ for (i = 0; i < count; i++) {
+ XiveIVE *ive = xive_get_ive(x, base + i);
+
+ ive->w = IVE_VALID | IVE_MASKED;
+ }
+ return base;
+}
+
+/*
* Main XIVE object
*/
@@ -69,6 +69,7 @@ void xive_spapr_init(sPAPRMachineState *spapr);
void xive_spapr_populate(XIVE *x, void *fdt);
void xive_mmio_map(XIVE *x);
+uint32_t xive_alloc_hw_irqs(XIVE *x, uint32_t count, uint32_t align);
void xive_ics_create(XiveICSState *xs, XIVE *x, uint32_t offset,
uint32_t nr_irqs, uint32_t shift, uint32_t flags,
The IRQ number allocator is inspired by OPAL which allocates IPI IRQ numbers from the bottom of the IRQ number space and allocates the HW IRQ numbers from the top. So, this might be slightly overkill for our need. Needs to be discussed. Signed-off-by: Cédric Le Goater <clg@kaod.org> --- hw/intc/xive.c | 53 +++++++++++++++++++++++++++++++++++++++++++++++++++ include/hw/ppc/xive.h | 1 + 2 files changed, 54 insertions(+)