From patchwork Thu Jun 29 12:41:44 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Llu=C3=ADs_Vilanova?= X-Patchwork-Id: 782218 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3wyzp41Mvhz9s3T for ; Thu, 29 Jun 2017 22:42:35 +1000 (AEST) Received: from localhost ([::1]:39035 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dQYmF-0005wn-SI for incoming@patchwork.ozlabs.org; Thu, 29 Jun 2017 08:42:31 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:34212) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dQYls-0005vR-Fa for qemu-devel@nongnu.org; Thu, 29 Jun 2017 08:42:12 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dQYlm-0008Tf-CJ for qemu-devel@nongnu.org; Thu, 29 Jun 2017 08:42:08 -0400 Received: from roura.ac.upc.edu ([147.83.33.10]:52875 helo=roura.ac.upc.es) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dQYlg-0008Ne-37; Thu, 29 Jun 2017 08:41:56 -0400 Received: from correu-1.ac.upc.es (correu-1.ac.upc.es [147.83.30.91]) by roura.ac.upc.es (8.13.8/8.13.8) with ESMTP id v5TCfpRx028371; Thu, 29 Jun 2017 14:41:53 +0200 Received: from localhost (unknown [132.68.50.243]) by correu-1.ac.upc.es (Postfix) with ESMTPSA id BEE841C4; Thu, 29 Jun 2017 14:41:45 +0200 (CEST) From: =?utf-8?b?TGx1w61z?= Vilanova To: qemu-devel@nongnu.org Date: Thu, 29 Jun 2017 15:41:44 +0300 Message-Id: <149874010452.9180.5182724462159161565.stgit@frigg.lan> X-Mailer: git-send-email 2.11.0 In-Reply-To: <149873841036.9180.16600465902334229930.stgit@frigg.lan> References: <149873841036.9180.16600465902334229930.stgit@frigg.lan> User-Agent: StGit/0.17.1-dirty MIME-Version: 1.0 X-MIME-Autoconverted: from 8bit to quoted-printable by roura.ac.upc.es id v5TCfpRx028371 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6.x [fuzzy] X-Received-From: 147.83.33.10 Subject: [Qemu-devel] [PATCH v10 7/7] trace: [trivial] Statically enable all guest events X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Eduardo Habkost , "open list:Trivial patches" , Michael Tokarev , Laurent Vivier , "Emilio G. Cota" , Stefan Hajnoczi Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" The existing optimizations makes it feasible to have them available on all builds. Some quick'n'dirty numbers with 400.perlbench (SPECcpu2006) on the train input (medium size - suns.pl) and the guest_mem_before event: * vanilla, statically disabled real 0m2,259s user 0m2,252s sys 0m0,004s * vanilla, statically enabled (overhead: 2.18x) real 0m4,921s user 0m4,912s sys 0m0,008s * multi-tb, statically disabled (overhead: 0.99x) [within noise range] real 0m2,228s user 0m2,216s sys 0m0,008s * multi-tb, statically enabled (overhead: 0.99x) [within noise range] real 0m2,229s user 0m2,224s sys 0m0,004s Now enabling all events when booting an ARM system that immediately shuts down (https://lists.gnu.org/archive/html/qemu-devel/2017-06/msg04085.html): * vanilla, statically disabled real 0m32,153s user 0m31,276s sys 0m0,108s * vanilla, statically enabled (overhead: 1.35x) real 0m43,507s user 0m42,680s sys 0m0,168s * multi-tb, statically disabled (overhead: 1.03x) real 0m32,993s user 0m32,516s sys 0m0,104s * multi-tb, statically enabled (overhead: 1.00x) [within noise range] real 0m32,110s user 0m31,176s sys 0m0,156s And finally enabling all events using Emilio's dbt-bench (where orig == vanilla, new == multi-tb): NBench score; higher is better 180 +-+--------+----------+----------+---------+----------+----------+----------+----------+----------+---------+----------+--------+-+ | | | *** $$$$%% orig | 160 +-+....................................*.*.$..$.%............................................................orig-enabled +-+ | * * $ $ % new | 140 +-+....................................*.*.$..$.%............................................................new-disabled.......+-+ | * * $ $ % | | * * $ $ % | 120 +-+....................................*.*.$..$.%...............................................................................+-+ | * * $ $ % | | * * $ $ % | 100 +-+....................................*.*.$..$.%.....$$$%%%....................................................................+-+ | * * $ $ % *** $ $ % *** $$$%% | 80 +-+....................................*.*.$..$.%.*.*.$.$..%.*.*.$.$.%..........................................................+-+ | * * $ $ % * * $ $ % * * $ $ % | | * * $ $ % * * $ $ % * * $ $ % | 60 +-+.........................***..$$$%%.*.*##..$.%.*.*.$.$..%.*.*.$.$.%..***.$$$%%...............................................+-+ | **** $$$%% * * $ $ % * * # $ % * *## $ % * * $ $ % * * $ $ % | | * * $ $ % * * $ $ % * * # $ % * * # $ % * *## $ % * * $ $ % | 40 +-+..............*..*.$.$.%.*.*..$.$.%.*.*.#..$.%.*.*.#.$..%.*.*.#.$.%..*.*.$.$.%...............................................+-+ | * * $ $ % * * $ $ % * * # $ % * * # $ % * * # $ % * *## $ % *** $$$%%% | 20 +-+....***.$$$%%.*..*##.$.%.*.*###.$.%.*.*.#..$.%.*.*.#.$..%.*.*.#.$.%..*.*.#.$.%..................................*.*.$.$..%...+-+ | * *## $ % * * # $ % * * # $ % * * # $ % * * # $ % * * # $ % * * # $ % * *## $ % | | * * # $ % * * # $ % * * # $ % * * # $ % * * # $ % * * # $ % * * # $ % ***###$$%% ***##$$$%% * * # $ % | 0 +-+----***##$$%%-****##$$%%-***###$$%%-***##$$$%%-***##$$%%%-***##$$%%--***##$$%%-****##$$%%-***###$$%%-***##$$$%%-***##$$%%%---+-+ NUMERIC SORTSTRING SORT BITFIEFP EMULATION ASSIGNMENT IDEA HUFFMAN FOURIER NEURLU DECOMPOSITION gmean png: http://imgur.com/a/8XG5S Signed-off-by: Lluís Vilanova Reviewed-by: Emilio G. Cota --- trace-events | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/trace-events b/trace-events index bae63fdb1d..f9dbd7f509 100644 --- a/trace-events +++ b/trace-events @@ -106,7 +106,7 @@ vcpu guest_cpu_reset(void) # # Mode: user, softmmu # Targets: TCG(all) -disable vcpu tcg guest_mem_before(TCGv vaddr, uint8_t info) "info=%d", "vaddr=0x%016"PRIx64" info=%d" +vcpu tcg guest_mem_before(TCGv vaddr, uint8_t info) "info=%d", "vaddr=0x%016"PRIx64" info=%d" # @num: System call number. # @arg*: System call argument value. @@ -115,7 +115,7 @@ disable vcpu tcg guest_mem_before(TCGv vaddr, uint8_t info) "info=%d", "vaddr=0x # # Mode: user # Targets: TCG(all) -disable vcpu guest_user_syscall(uint64_t num, uint64_t arg1, uint64_t arg2, uint64_t arg3, uint64_t arg4, uint64_t arg5, uint64_t arg6, uint64_t arg7, uint64_t arg8) "num=0x%016"PRIx64" arg1=0x%016"PRIx64" arg2=0x%016"PRIx64" arg3=0x%016"PRIx64" arg4=0x%016"PRIx64" arg5=0x%016"PRIx64" arg6=0x%016"PRIx64" arg7=0x%016"PRIx64" arg8=0x%016"PRIx64 +vcpu guest_user_syscall(uint64_t num, uint64_t arg1, uint64_t arg2, uint64_t arg3, uint64_t arg4, uint64_t arg5, uint64_t arg6, uint64_t arg7, uint64_t arg8) "num=0x%016"PRIx64" arg1=0x%016"PRIx64" arg2=0x%016"PRIx64" arg3=0x%016"PRIx64" arg4=0x%016"PRIx64" arg5=0x%016"PRIx64" arg6=0x%016"PRIx64" arg7=0x%016"PRIx64" arg8=0x%016"PRIx64 # @num: System call number. # @ret: System call result value. @@ -124,4 +124,4 @@ disable vcpu guest_user_syscall(uint64_t num, uint64_t arg1, uint64_t arg2, uint # # Mode: user # Targets: TCG(all) -disable vcpu guest_user_syscall_ret(uint64_t num, uint64_t ret) "num=0x%016"PRIx64" ret=0x%016"PRIx64 +vcpu guest_user_syscall_ret(uint64_t num, uint64_t ret) "num=0x%016"PRIx64" ret=0x%016"PRIx64