From patchwork Thu Jun 29 05:49:52 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lan Tianyu X-Patchwork-Id: 782191 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3wyyr24cQGz9s76 for ; Thu, 29 Jun 2017 21:59:14 +1000 (AEST) Received: from localhost ([::1]:38513 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dQY6J-0008Kp-2F for incoming@patchwork.ozlabs.org; Thu, 29 Jun 2017 07:59:11 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:43988) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dQY3y-0006kr-FW for qemu-devel@nongnu.org; Thu, 29 Jun 2017 07:56:47 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dQY3v-000731-7M for qemu-devel@nongnu.org; Thu, 29 Jun 2017 07:56:46 -0400 Received: from mga14.intel.com ([192.55.52.115]:52319) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dQY3u-00071P-Uh for qemu-devel@nongnu.org; Thu, 29 Jun 2017 07:56:43 -0400 Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga103.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 29 Jun 2017 04:56:42 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.40,280,1496127600"; d="scan'208";a="120301500" Received: from sky-ws.sh.intel.com (HELO localhost) ([10.239.48.74]) by fmsmga005.fm.intel.com with ESMTP; 29 Jun 2017 04:56:40 -0700 From: Lan Tianyu To: qemu-devel@nongnu.org, xen-devel@lists.xensource.com Date: Thu, 29 Jun 2017 01:49:52 -0400 Message-Id: <1498715394-16402-2-git-send-email-tianyu.lan@intel.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1498715394-16402-1-git-send-email-tianyu.lan@intel.com> References: <1498715394-16402-1-git-send-email-tianyu.lan@intel.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 192.55.52.115 Subject: [Qemu-devel] [PATCH 1/3] i386/msi: Correct mask of destination ID in MSI address X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Lan Tianyu , kevin.tian@intel.com, sstabellini@kernel.org, mst@redhat.com, anthony.perard@citrix.com, marcel@redhat.com, Chao Gao Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Chao Gao According to SDM 10.11.1, only [19:12] bits of MSI address are Destination ID, change the mask to avoid ambiguity for VT-d spec has used the bit 4 to indicate a remappable interrupt request. Signed-off-by: Chao Gao Signed-off-by: Lan Tianyu Reviewed-by: Anthony PERARD Reviewed-by: Peter Xu --- include/hw/i386/apic-msidef.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/hw/i386/apic-msidef.h b/include/hw/i386/apic-msidef.h index 8b4d4cc..420b411 100644 --- a/include/hw/i386/apic-msidef.h +++ b/include/hw/i386/apic-msidef.h @@ -26,6 +26,6 @@ #define MSI_ADDR_DEST_ID_SHIFT 12 #define MSI_ADDR_DEST_IDX_SHIFT 4 -#define MSI_ADDR_DEST_ID_MASK 0x00ffff0 +#define MSI_ADDR_DEST_ID_MASK 0x000ff000 #endif /* HW_APIC_MSIDEF_H */