From patchwork Wed Jun 28 12:57:00 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Llu=C3=ADs_Vilanova?= X-Patchwork-Id: 781680 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3wyNKL4Bbqz9s7m for ; Wed, 28 Jun 2017 23:04:06 +1000 (AEST) Received: from localhost ([::1]:33270 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dQCdY-0007Zw-5w for incoming@patchwork.ozlabs.org; Wed, 28 Jun 2017 09:04:04 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:49604) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dQCWy-0001yY-Du for qemu-devel@nongnu.org; Wed, 28 Jun 2017 08:57:17 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dQCWt-0005XA-Hy for qemu-devel@nongnu.org; Wed, 28 Jun 2017 08:57:16 -0400 Received: from roura.ac.upc.es ([147.83.33.10]:54527) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dQCWt-0005Wu-4z for qemu-devel@nongnu.org; Wed, 28 Jun 2017 08:57:11 -0400 Received: from correu-1.ac.upc.es (correu-1.ac.upc.es [147.83.30.91]) by roura.ac.upc.es (8.13.8/8.13.8) with ESMTP id v5SCv7cL026592; Wed, 28 Jun 2017 14:57:07 +0200 Received: from localhost (unknown [132.68.50.243]) by correu-1.ac.upc.es (Postfix) with ESMTPSA id 003901C4; Wed, 28 Jun 2017 14:57:01 +0200 (CEST) From: =?utf-8?b?TGx1w61z?= Vilanova To: qemu-devel@nongnu.org Date: Wed, 28 Jun 2017 15:57:00 +0300 Message-Id: <149865462073.17063.17488435214703164893.stgit@frigg.lan> X-Mailer: git-send-email 2.11.0 In-Reply-To: <149865219962.17063.10630533069463266646.stgit@frigg.lan> References: <149865219962.17063.10630533069463266646.stgit@frigg.lan> User-Agent: StGit/0.17.1-dirty MIME-Version: 1.0 X-MIME-Autoconverted: from 8bit to quoted-printable by roura.ac.upc.es id v5SCv7cL026592 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6.x [fuzzy] X-Received-From: 147.83.33.10 Subject: [Qemu-devel] [PATCH v11 10/29] target/i386: [tcg] Refactor translate_insn X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Eduardo Habkost , Peter Crosthwaite , "Emilio G. Cota" , Paolo Bonzini , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Richard Henderson Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Incrementally paves the way towards using the generic instruction translation loop. Signed-off-by: Lluís Vilanova Reviewed-by: Emilio G. Cota Reviewed-by: Richard Henderson --- target/i386/translate.c | 72 +++++++++++++++++++++++++++++++---------------- 1 file changed, 48 insertions(+), 24 deletions(-) diff --git a/target/i386/translate.c b/target/i386/translate.c index 3eee348de7..da4b409d97 100644 --- a/target/i386/translate.c +++ b/target/i386/translate.c @@ -4420,15 +4420,17 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b, /* convert one instruction. s->base.is_jmp is set if the translation must be stopped. Return the next pc value */ -static target_ulong disas_insn(CPUX86State *env, DisasContext *s, - target_ulong pc_start) +static target_ulong disas_insn(DisasContextBase *dcbase, CPUState *cpu) { + DisasContext *s = container_of(dcbase, DisasContext, base); + CPUX86State *env = cpu->env_ptr; int b, prefixes; int shift; TCGMemOp ot, aflag, dflag; int modrm, reg, rm, mod, op, opreg, val; target_ulong next_eip, tval; int rex_w, rex_r; + target_ulong pc_start = s->base.pc_next; s->pc_start = s->pc = pc_start; prefixes = 0; @@ -8478,10 +8480,51 @@ static BreakpointCheckType i386_trblock_breakpoint_check( } } +static target_ulong i386_trblock_translate_insn(DisasContextBase *dcbase, + CPUState *cpu) +{ + DisasContext *dc = container_of(dcbase, DisasContext, base); + target_ulong pc_next = disas_insn(&dc->base, cpu); + + if (dc->base.is_jmp) { + return pc_next; + } + + if (dc->tf || (dc->base.tb->flags & HF_INHIBIT_IRQ_MASK)) { + /* if single step mode, we generate only one instruction and + generate an exception */ + /* if irq were inhibited with HF_INHIBIT_IRQ_MASK, we clear + the flag and abort the translation to give the irqs a + change to be happen */ + gen_jmp_im(pc_next - dc->cs_base); + gen_eob(dc); + dc->base.is_jmp = DISAS_TOO_MANY; + } else if ((dc->base.tb->cflags & CF_USE_ICOUNT) + && ((dc->base.pc_next & TARGET_PAGE_MASK) + != ((dc->base.pc_next + TARGET_MAX_INSN_SIZE - 1) + & TARGET_PAGE_MASK) + || (dc->base.pc_next & ~TARGET_PAGE_MASK) == 0)) { + /* Do not cross the boundary of the pages in icount mode, + it can cause an exception. Do it only when boundary is + crossed by the first instruction in the block. + If current instruction already crossed the bound - it's ok, + because an exception hasn't stopped this code. + */ + gen_jmp_im(pc_next - dc->cs_base); + gen_eob(dc); + dc->base.is_jmp = DISAS_TOO_MANY; + } else if ((pc_next - dc->base.pc_first) >= (TARGET_PAGE_SIZE - 32)) { + gen_jmp_im(pc_next - dc->cs_base); + gen_eob(dc); + dc->base.is_jmp = DISAS_TOO_MANY; + } + + return pc_next; +} + /* generate intermediate code for basic block 'tb'. */ void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb) { - CPUX86State *env = cpu->env_ptr; DisasContext dc1, *dc = &dc1; int num_insns; int max_insns; @@ -8543,39 +8586,20 @@ void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb) gen_io_start(); } - dc->base.pc_next = disas_insn(env, dc, dc->base.pc_next); + dc->base.pc_next = i386_trblock_translate_insn(&dc->base, cpu); /* stop translation if indicated */ if (dc->base.is_jmp) { break; } /* if single step mode, we generate only one instruction and generate an exception */ - /* if irq were inhibited with HF_INHIBIT_IRQ_MASK, we clear - the flag and abort the translation to give the irqs a - change to be happen */ - if (dc->tf || dc->base.singlestep_enabled || - (dc->base.tb->flags & HF_INHIBIT_IRQ_MASK)) { - gen_jmp_im(dc->base.pc_next - dc->cs_base); - gen_eob(dc); - break; - } - /* Do not cross the boundary of the pages in icount mode, - it can cause an exception. Do it only when boundary is - crossed by the first instruction in the block. - If current instruction already crossed the bound - it's ok, - because an exception hasn't stopped this code. - */ - if ((tb->cflags & CF_USE_ICOUNT) - && ((dc->base.pc_next & TARGET_PAGE_MASK) - != ((dc->base.pc_next + TARGET_MAX_INSN_SIZE - 1) & TARGET_PAGE_MASK) - || (dc->base.pc_next & ~TARGET_PAGE_MASK) == 0)) { + if (dc->base.singlestep_enabled) { gen_jmp_im(dc->base.pc_next - dc->cs_base); gen_eob(dc); break; } /* if too long translation, stop generation too */ if (tcg_op_buf_full() || - (dc->base.pc_next - dc->base.pc_first) >= (TARGET_PAGE_SIZE - 32) || num_insns >= max_insns) { gen_jmp_im(dc->base.pc_next - dc->cs_base); gen_eob(dc);