From patchwork Tue Apr 25 11:26:04 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Jason Wang X-Patchwork-Id: 754754 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3wC1C95767z9s80 for ; Tue, 25 Apr 2017 21:27:17 +1000 (AEST) Received: from localhost ([::1]:48570 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1d2ycl-0006eO-55 for incoming@patchwork.ozlabs.org; Tue, 25 Apr 2017 07:27:15 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36673) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1d2yc5-0006cZ-VA for qemu-devel@nongnu.org; Tue, 25 Apr 2017 07:26:34 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1d2yc4-0002AN-Pv for qemu-devel@nongnu.org; Tue, 25 Apr 2017 07:26:33 -0400 Received: from mx1.redhat.com ([209.132.183.28]:47308) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1d2yc4-00029e-Fq for qemu-devel@nongnu.org; Tue, 25 Apr 2017 07:26:32 -0400 Received: from smtp.corp.redhat.com (int-mx01.intmail.prod.int.phx2.redhat.com [10.5.11.11]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 704B63D943; Tue, 25 Apr 2017 11:26:31 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mx1.redhat.com 704B63D943 Authentication-Results: ext-mx06.extmail.prod.ext.phx2.redhat.com; dmarc=none (p=none dis=none) header.from=redhat.com Authentication-Results: ext-mx06.extmail.prod.ext.phx2.redhat.com; spf=pass smtp.mailfrom=jasowang@redhat.com DKIM-Filter: OpenDKIM Filter v2.11.0 mx1.redhat.com 704B63D943 Received: from jason-ThinkPad-T450s.redhat.com (ovpn-8-52.pek2.redhat.com [10.72.8.52]) by smtp.corp.redhat.com (Postfix) with ESMTP id 9A12C84DA5; Tue, 25 Apr 2017 11:26:25 +0000 (UTC) From: Jason Wang To: peter.maydell@linaro.org, qemu-devel@nongnu.org Date: Tue, 25 Apr 2017 19:26:04 +0800 Message-Id: <1493119568-15218-5-git-send-email-jasowang@redhat.com> In-Reply-To: <1493119568-15218-1-git-send-email-jasowang@redhat.com> References: <1493119568-15218-1-git-send-email-jasowang@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.11 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.30]); Tue, 25 Apr 2017 11:26:31 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [PULL V2 4/8] net/ftgmac100: add a 'aspeed' property X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jason Wang , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Cédric Le Goater The Aspeed SoCs have a different definition of the end of the ring buffer bit. Add a property to specify which set of bits should be used by the NIC. Signed-off-by: Cédric Le Goater Signed-off-by: Jason Wang --- hw/net/ftgmac100.c | 17 +++++++++++++++-- include/hw/net/ftgmac100.h | 4 ++++ 2 files changed, 19 insertions(+), 2 deletions(-) diff --git a/hw/net/ftgmac100.c b/hw/net/ftgmac100.c index c35f368..3c36ab9 100644 --- a/hw/net/ftgmac100.c +++ b/hw/net/ftgmac100.c @@ -126,6 +126,7 @@ #define FTGMAC100_TXDES0_CRC_ERR (1 << 19) #define FTGMAC100_TXDES0_LTS (1 << 28) #define FTGMAC100_TXDES0_FTS (1 << 29) +#define FTGMAC100_TXDES0_EDOTR_ASPEED (1 << 30) #define FTGMAC100_TXDES0_TXDMA_OWN (1 << 31) #define FTGMAC100_TXDES1_VLANTAG_CI(x) ((x) & 0xffff) @@ -154,6 +155,7 @@ #define FTGMAC100_RXDES0_PAUSE_FRAME (1 << 25) #define FTGMAC100_RXDES0_LRS (1 << 28) #define FTGMAC100_RXDES0_FRS (1 << 29) +#define FTGMAC100_RXDES0_EDORR_ASPEED (1 << 30) #define FTGMAC100_RXDES0_RXPKT_RDY (1 << 31) #define FTGMAC100_RXDES1_VLANTAG_CI 0xffff @@ -462,7 +464,7 @@ static void ftgmac100_do_tx(FTGMAC100State *s, uint32_t tx_ring, /* Write back the modified descriptor. */ ftgmac100_write_bd(&bd, addr); /* Advance to the next descriptor. */ - if (bd.des0 & FTGMAC100_TXDES0_EDOTR) { + if (bd.des0 & s->txdes0_edotr) { addr = tx_ring; } else { addr += sizeof(FTGMAC100Desc); @@ -880,7 +882,7 @@ static ssize_t ftgmac100_receive(NetClientState *nc, const uint8_t *buf, s->isr |= FTGMAC100_INT_RPKT_FIFO; } ftgmac100_write_bd(&bd, addr); - if (bd.des0 & FTGMAC100_RXDES0_EDORR) { + if (bd.des0 & s->rxdes0_edorr) { addr = s->rx_ring; } else { addr += sizeof(FTGMAC100Desc); @@ -921,6 +923,14 @@ static void ftgmac100_realize(DeviceState *dev, Error **errp) FTGMAC100State *s = FTGMAC100(dev); SysBusDevice *sbd = SYS_BUS_DEVICE(dev); + if (s->aspeed) { + s->txdes0_edotr = FTGMAC100_TXDES0_EDOTR_ASPEED; + s->rxdes0_edorr = FTGMAC100_RXDES0_EDORR_ASPEED; + } else { + s->txdes0_edotr = FTGMAC100_TXDES0_EDOTR; + s->rxdes0_edorr = FTGMAC100_RXDES0_EDORR; + } + memory_region_init_io(&s->iomem, OBJECT(dev), &ftgmac100_ops, s, TYPE_FTGMAC100, 0x2000); sysbus_init_mmio(sbd, &s->iomem); @@ -967,11 +977,14 @@ static const VMStateDescription vmstate_ftgmac100 = { VMSTATE_UINT32(phy_advertise, FTGMAC100State), VMSTATE_UINT32(phy_int, FTGMAC100State), VMSTATE_UINT32(phy_int_mask, FTGMAC100State), + VMSTATE_UINT32(txdes0_edotr, FTGMAC100State), + VMSTATE_UINT32(rxdes0_edorr, FTGMAC100State), VMSTATE_END_OF_LIST() } }; static Property ftgmac100_properties[] = { + DEFINE_PROP_BOOL("aspeed", FTGMAC100State, aspeed, false), DEFINE_NIC_PROPERTIES(FTGMAC100State, conf), DEFINE_PROP_END_OF_LIST(), }; diff --git a/include/hw/net/ftgmac100.h b/include/hw/net/ftgmac100.h index 962a718..d9bc589 100644 --- a/include/hw/net/ftgmac100.h +++ b/include/hw/net/ftgmac100.h @@ -55,6 +55,10 @@ typedef struct FTGMAC100State { uint32_t phy_advertise; uint32_t phy_int; uint32_t phy_int_mask; + + bool aspeed; + uint32_t txdes0_edotr; + uint32_t rxdes0_edorr; } FTGMAC100State; #endif