From patchwork Wed Apr 19 17:41:22 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aaron Lindsay X-Patchwork-Id: 752400 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3w7V2W630qz9s65 for ; Thu, 20 Apr 2017 03:52:35 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=codeaurora.org header.i=@codeaurora.org header.b="Bos8ZdxU"; dkim=fail reason="signature verification failed" (1024-bit key) header.d=codeaurora.org header.i=@codeaurora.org header.b="Bos8ZdxU"; dkim-atps=neutral Received: from localhost ([::1]:49671 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1d0tmL-0008UC-Af for incoming@patchwork.ozlabs.org; Wed, 19 Apr 2017 13:52:33 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:44174) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1d0tcC-0008NP-Hu for qemu-devel@nongnu.org; Wed, 19 Apr 2017 13:42:05 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1d0tcB-0004Te-FT for qemu-devel@nongnu.org; Wed, 19 Apr 2017 13:42:04 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:37964) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1d0tc6-0004Q9-NL; Wed, 19 Apr 2017 13:41:58 -0400 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id D86A6610DB; Wed, 19 Apr 2017 17:41:57 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1492623717; bh=qzlOI4KsqbIoOUzvLEVRckt/vWdX5oUMMBZks/dg04o=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Bos8ZdxU/7uw6+nP6LpXysDnLInvoaf7pAbOlOFw1bRCQKphd8v8MpXRxjcjPwqe+ x9Y/rUDmuPlHrhocQWxHCHpAK3rAMhbTpakG2DQ22Qti7/hppmsz2JUz7+xwAgOcJZ 8yKnpzJ2yXaj+FhklG5ToYwd2aPc+UJWKvnHJ2Cs= Received: from mossypile.qualcomm.com (global_nat1_iad_fw.qualcomm.com [129.46.232.65]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: alindsay@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 8DE1F6110B; Wed, 19 Apr 2017 17:41:56 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1492623717; bh=qzlOI4KsqbIoOUzvLEVRckt/vWdX5oUMMBZks/dg04o=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Bos8ZdxU/7uw6+nP6LpXysDnLInvoaf7pAbOlOFw1bRCQKphd8v8MpXRxjcjPwqe+ x9Y/rUDmuPlHrhocQWxHCHpAK3rAMhbTpakG2DQ22Qti7/hppmsz2JUz7+xwAgOcJZ 8yKnpzJ2yXaj+FhklG5ToYwd2aPc+UJWKvnHJ2Cs= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 8DE1F6110B Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=alindsay@codeaurora.org From: Aaron Lindsay To: Peter Maydell , qemu-arm@nongnu.org Date: Wed, 19 Apr 2017 13:41:22 -0400 Message-Id: <1492623684-25799-12-git-send-email-alindsay@codeaurora.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1492623684-25799-1-git-send-email-alindsay@codeaurora.org> References: <1492623684-25799-1-git-send-email-alindsay@codeaurora.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 198.145.29.96 Subject: [Qemu-devel] [PATCH 11/13] target/arm: PMU: Add instruction and cycle events X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mspradli@codeaurora.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" The instruction event is only enabled when icount is used, cycles are always supported. Note: Setting can_do_io=1 should not be done here. It is ugly and wrong, but I am not sure of the proper way to handle this (See 'target/arm: Filter cycle counter based on PMCCFILTR_EL0') Signed-off-by: Aaron Lindsay --- target/arm/helper.c | 49 +++++++++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 47 insertions(+), 2 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 66e576a..5972984 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -14,6 +14,7 @@ #include "arm_ldst.h" #include /* For crc32 */ #include "exec/semihost.h" +#include "sysemu/cpus.h" #include "sysemu/kvm.h" #define ARM_CPU_FREQ 1000000000 /* FIXME: 1 GHz, should be configurable */ @@ -901,8 +902,53 @@ typedef struct pm_event { uint64_t (*get_count)(CPUARMState *); } pm_event; +static bool event_always_supported(CPUARMState *env) +{ + return true; +} + +static uint64_t cycles_get_count(CPUARMState *env) +{ + uint64_t ret; + CPUState *cpu = ENV_GET_CPU(env); + uint32_t saved_can_do_io = cpu->can_do_io; + cpu->can_do_io = 1; + + ret = muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), + ARM_CPU_FREQ, NANOSECONDS_PER_SECOND); + + cpu->can_do_io = saved_can_do_io; + return ret; +} + +static bool instructions_supported(CPUARMState *env) +{ + return use_icount == 1 /* Precise instruction counting */; +} + +static uint64_t instructions_get_count(CPUARMState *env) +{ + uint64_t ret; + CPUState *cpu = ENV_GET_CPU(env); + uint32_t saved_can_do_io = cpu->can_do_io; + cpu->can_do_io = 1; + + ret = (uint64_t)cpu_get_icount_raw(); + + cpu->can_do_io = saved_can_do_io; + return ret; +} + #define SUPPORTED_EVENT_SENTINEL UINT16_MAX static const pm_event pm_events[] = { + { .number = 0x008, /* INST_RETIRED */ + .supported = instructions_supported, + .get_count = instructions_get_count + }, + { .number = 0x011, /* CPU_CYCLES */ + .supported = event_always_supported, + .get_count = cycles_get_count + }, { .number = SUPPORTED_EVENT_SENTINEL } }; static uint16_t supported_event_map[0x3f]; @@ -1087,8 +1133,7 @@ void pmccntr_sync(CPUARMState *env) !pmu_counter_filtered(env, env->cp15.pmccfiltr_el0)) { uint64_t temp_ticks; - temp_ticks = muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), - ARM_CPU_FREQ, NANOSECONDS_PER_SECOND); + temp_ticks = cycles_get_count(env); if (env->cp15.c9_pmcr & PMCRD) { /* Increment once every 64 processor clock cycles */