From patchwork Wed Apr 5 12:41:29 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?C=C3=A9dric_Le_Goater?= X-Patchwork-Id: 747259 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3vylr03QNxz9s89 for ; Wed, 5 Apr 2017 22:43:12 +1000 (AEST) Received: from localhost ([::1]:40318 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cvkHG-00088j-0Q for incoming@patchwork.ozlabs.org; Wed, 05 Apr 2017 08:43:10 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:41752) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cvkGf-00086e-ML for qemu-devel@nongnu.org; Wed, 05 Apr 2017 08:42:36 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1cvkGb-00014j-Pl for qemu-devel@nongnu.org; Wed, 05 Apr 2017 08:42:33 -0400 Received: from 4.mo177.mail-out.ovh.net ([46.105.37.72]:48764) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1cvkGb-00014J-Jd for qemu-devel@nongnu.org; Wed, 05 Apr 2017 08:42:29 -0400 Received: from player688.ha.ovh.net (b6.ovh.net [213.186.33.56]) by mo177.mail-out.ovh.net (Postfix) with ESMTP id 3391349D35 for ; Wed, 5 Apr 2017 14:42:28 +0200 (CEST) Received: from zorba.kaod.org.com (LFbn-1-10647-27.w90-89.abo.wanadoo.fr [90.89.233.27]) (Authenticated sender: clg@kaod.org) by player688.ha.ovh.net (Postfix) with ESMTPSA id 0E20D20097; Wed, 5 Apr 2017 14:42:23 +0200 (CEST) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: David Gibson Date: Wed, 5 Apr 2017 14:41:29 +0200 Message-Id: <1491396106-26376-5-git-send-email-clg@kaod.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1491396106-26376-1-git-send-email-clg@kaod.org> References: <1491396106-26376-1-git-send-email-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 16587883329344539622 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrfeeliedrtddvgdehhecutefuodetggdotefrodftvfcurfhrohhfihhlvgemucfqggfjpdevjffgvefmvefgnecuuegrihhlohhuthemuceftddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmd X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 46.105.37.72 Subject: [Qemu-devel] [PATCH 04/21] ppc/pnv: enable only one LPC bus X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, qemu-devel@nongnu.org, =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Multi chip systems only have one LPC bus, on chip 0. The PnvLPC object will still be created under the PnvChip objects but only the one under chip 0 will be advertise in the device tree. Also remove the comment which is slightly wrong. Only chip 0 has a LPC device node : xscom@3fc0000000000/isa@b0020 Signed-off-by: Cédric Le Goater Cc: Benjamin Herrenschmidt --- hw/ppc/pnv.c | 2 ++ hw/ppc/pnv_lpc.c | 20 ++++++++++++-------- include/hw/ppc/pnv_lpc.h | 2 ++ 3 files changed, 16 insertions(+), 8 deletions(-) diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index 78133e5d20e1..493c7eed7980 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -811,6 +811,8 @@ static void pnv_chip_realize(DeviceState *dev, Error **errp) g_free(typename); /* Create LPC controller */ + object_property_set_int(OBJECT(&chip->lpc), chip->chip_id, "chip-id", + &error_fatal); object_property_set_bool(OBJECT(&chip->lpc), true, "realized", &error_fatal); pnv_xscom_add_subregion(chip, PNV_XSCOM_LPC_BASE, &chip->lpc.xscom_regs); diff --git a/hw/ppc/pnv_lpc.c b/hw/ppc/pnv_lpc.c index 20cbb6a0dbbd..1a212a2a399f 100644 --- a/hw/ppc/pnv_lpc.c +++ b/hw/ppc/pnv_lpc.c @@ -92,14 +92,6 @@ enum { #define LPC_HC_REGS_OPB_SIZE 0x00001000 -/* - * TODO: the "primary" cell should only be added on chip 0. This is - * how skiboot chooses the default LPC controller on multichip - * systems. - * - * It would be easly done if we can change the populate() interface to - * replace the PnvXScomInterface parameter by a PnvChip one - */ static int pnv_lpc_populate(PnvXScomInterface *dev, void *fdt, int xscom_offset) { const char compat[] = "ibm,power8-lpc\0ibm,lpc"; @@ -110,6 +102,12 @@ static int pnv_lpc_populate(PnvXScomInterface *dev, void *fdt, int xscom_offset) cpu_to_be32(lpc_pcba), cpu_to_be32(PNV_XSCOM_LPC_SIZE) }; + PnvLpcController *lpc = PNV_LPC(dev); + + /* Only populate one LPC bus per system, the one on chip 0.*/ + if (lpc->chip_id) { + return 0; + } name = g_strdup_printf("isa@%x", lpc_pcba); offset = fdt_add_subnode(fdt, xscom_offset, name); @@ -486,6 +484,11 @@ static void pnv_lpc_realize(DeviceState *dev, Error **errp) lpc->psi = PNV_PSI(obj); } +static Property pnv_lpc_properties[] = { + DEFINE_PROP_UINT32("chip-id", PnvLpcController, chip_id, 0), + DEFINE_PROP_END_OF_LIST(), +}; + static void pnv_lpc_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); @@ -494,6 +497,7 @@ static void pnv_lpc_class_init(ObjectClass *klass, void *data) xdc->populate = pnv_lpc_populate; dc->realize = pnv_lpc_realize; + dc->props = pnv_lpc_properties; } static const TypeInfo pnv_lpc_info = { diff --git a/include/hw/ppc/pnv_lpc.h b/include/hw/ppc/pnv_lpc.h index 53040026c37b..dcfadda90090 100644 --- a/include/hw/ppc/pnv_lpc.h +++ b/include/hw/ppc/pnv_lpc.h @@ -67,6 +67,8 @@ typedef struct PnvLpcController { /* PSI to generate interrupts */ PnvPsi *psi; + + uint32_t chip_id; } PnvLpcController; #define LPC_HC_IRQ_SERIRQ0 0x80000000 /* all bits down to ... */