From patchwork Wed Mar 8 10:52:51 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?C=C3=A9dric_Le_Goater?= X-Patchwork-Id: 736525 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3vdVlv6n6hz9s8W for ; Wed, 8 Mar 2017 21:54:51 +1100 (AEDT) Received: from localhost ([::1]:55519 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1clZF3-0008JH-DR for incoming@patchwork.ozlabs.org; Wed, 08 Mar 2017 05:54:49 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:37224) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1clZDu-0007yC-S3 for qemu-devel@nongnu.org; Wed, 08 Mar 2017 05:53:42 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1clZDr-0003DN-NZ for qemu-devel@nongnu.org; Wed, 08 Mar 2017 05:53:38 -0500 Received: from 3.mo177.mail-out.ovh.net ([46.105.36.172]:43415) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1clZDr-0003Cf-F3 for qemu-devel@nongnu.org; Wed, 08 Mar 2017 05:53:35 -0500 Received: from player714.ha.ovh.net (b7.ovh.net [213.186.33.57]) by mo177.mail-out.ovh.net (Postfix) with ESMTP id DF25438686 for ; Wed, 8 Mar 2017 11:53:33 +0100 (CET) Received: from zorba.kaod.org.com (LFbn-1-10647-27.w90-89.abo.wanadoo.fr [90.89.233.27]) (Authenticated sender: clg@kaod.org) by player714.ha.ovh.net (Postfix) with ESMTPSA id B42D53C00A2; Wed, 8 Mar 2017 11:53:28 +0100 (CET) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: David Gibson Date: Wed, 8 Mar 2017 11:52:51 +0100 Message-Id: <1488970371-8865-9-git-send-email-clg@kaod.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1488970371-8865-1-git-send-email-clg@kaod.org> References: <1488970371-8865-1-git-send-email-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 16333711427478784998 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrfeelhedrgeeggddujecutefuodetggdotefrodftvfcurfhrohhfihhlvgemucfqggfjpdevjffgvefmvefgnecuuegrihhlohhuthemuceftddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmd X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 46.105.36.172 Subject: [Qemu-devel] [PATCH for-2.10 8/8] ppc/pnv: Add support for POWER8+ LPC Controller X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, qemu-devel@nongnu.org, =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Benjamin Herrenschmidt It adds the Naples chip which supports proper LPC interrupts via the LPC controller rather than via an external CPLD. Signed-off-by: Benjamin Herrenschmidt [clg: - updated for qemu-2.9 - ported on latest PowerNV patchset ] Signed-off-by: Cédric Le Goater Reviewed-by: David Gibson --- hw/ppc/pnv.c | 15 ++++++++++++++- hw/ppc/pnv_lpc.c | 47 +++++++++++++++++++++++++++++++++++++++++++++-- include/hw/ppc/pnv_lpc.h | 9 +++++++++ 3 files changed, 68 insertions(+), 3 deletions(-) diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index ca5a078bc6c6..65dfe5b4c97b 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -376,7 +376,14 @@ static void pnv_lpc_isa_irq_handler_cpld(void *opaque, int n, int level) static void pnv_lpc_isa_irq_handler(void *opaque, int n, int level) { - /* XXX TODO */ + PnvChip *chip = opaque; + PnvLpcController *lpc = &chip->lpc; + + /* The Naples HW latches the 1 levels, clearing is done by SW */ + if (level) { + lpc->lpc_hc_irqstat |= LPC_HC_IRQ_SERIRQ0 >> n; + pnv_lpc_eval_irqs(lpc); + } } static ISABus *pnv_isa_create(PnvChip *chip) @@ -719,6 +726,12 @@ static void pnv_chip_init(Object *obj) object_property_add_child(obj, "occ", OBJECT(&chip->occ), NULL); object_property_add_const_link(OBJECT(&chip->occ), "psi", OBJECT(&chip->psi), &error_abort); + + /* + * The LPC controller needs PSI to generate interrupts + */ + object_property_add_const_link(OBJECT(&chip->lpc), "psi", + OBJECT(&chip->psi), &error_abort); } static void pnv_chip_icp_realize(PnvChip *chip, Error **errp) diff --git a/hw/ppc/pnv_lpc.c b/hw/ppc/pnv_lpc.c index 78db52415b11..20cbb6a0dbbd 100644 --- a/hw/ppc/pnv_lpc.c +++ b/hw/ppc/pnv_lpc.c @@ -250,6 +250,34 @@ static const MemoryRegionOps pnv_lpc_xscom_ops = { .endianness = DEVICE_BIG_ENDIAN, }; +void pnv_lpc_eval_irqs(PnvLpcController *lpc) +{ + bool lpc_to_opb_irq = false; + + /* Update LPC controller to OPB line */ + if (lpc->lpc_hc_irqser_ctrl & LPC_HC_IRQSER_EN) { + uint32_t irqs; + + irqs = lpc->lpc_hc_irqstat & lpc->lpc_hc_irqmask; + lpc_to_opb_irq = (irqs != 0); + } + + /* We don't honor the polarity register, it's pointless and unused + * anyway + */ + if (lpc_to_opb_irq) { + lpc->opb_irq_input |= OPB_MASTER_IRQ_LPC; + } else { + lpc->opb_irq_input &= ~OPB_MASTER_IRQ_LPC; + } + + /* Update OPB internal latch */ + lpc->opb_irq_stat |= lpc->opb_irq_input & lpc->opb_irq_mask; + + /* Reflect the interrupt */ + pnv_psi_irq_set(lpc->psi, PSIHB_IRQ_LPC_I2C, lpc->opb_irq_stat != 0); +} + static uint64_t lpc_hc_read(void *opaque, hwaddr addr, unsigned size) { PnvLpcController *lpc = opaque; @@ -300,12 +328,15 @@ static void lpc_hc_write(void *opaque, hwaddr addr, uint64_t val, break; case LPC_HC_IRQSER_CTRL: lpc->lpc_hc_irqser_ctrl = val; + pnv_lpc_eval_irqs(lpc); break; case LPC_HC_IRQMASK: lpc->lpc_hc_irqmask = val; + pnv_lpc_eval_irqs(lpc); break; case LPC_HC_IRQSTAT: lpc->lpc_hc_irqstat &= ~val; + pnv_lpc_eval_irqs(lpc); break; case LPC_HC_ERROR_ADDRESS: break; @@ -363,14 +394,15 @@ static void opb_master_write(void *opaque, hwaddr addr, switch (addr) { case OPB_MASTER_LS_IRQ_STAT: lpc->opb_irq_stat &= ~val; + pnv_lpc_eval_irqs(lpc); break; case OPB_MASTER_LS_IRQ_MASK: - /* XXX Filter out reserved bits */ lpc->opb_irq_mask = val; + pnv_lpc_eval_irqs(lpc); break; case OPB_MASTER_LS_IRQ_POL: - /* XXX Filter out reserved bits */ lpc->opb_irq_pol = val; + pnv_lpc_eval_irqs(lpc); break; case OPB_MASTER_LS_IRQ_INPUT: /* Read only */ @@ -398,6 +430,8 @@ static const MemoryRegionOps opb_master_ops = { static void pnv_lpc_realize(DeviceState *dev, Error **errp) { PnvLpcController *lpc = PNV_LPC(dev); + Object *obj; + Error *error = NULL; /* Reg inits */ lpc->lpc_hc_fw_rd_acc_size = LPC_HC_FW_RD_4B; @@ -441,6 +475,15 @@ static void pnv_lpc_realize(DeviceState *dev, Error **errp) pnv_xscom_region_init(&lpc->xscom_regs, OBJECT(dev), &pnv_lpc_xscom_ops, lpc, "xscom-lpc", PNV_XSCOM_LPC_SIZE); + + /* get PSI object from chip */ + obj = object_property_get_link(OBJECT(dev), "psi", &error); + if (!obj) { + error_setg(errp, "%s: required link 'psi' not found: %s", + __func__, error_get_pretty(error)); + return; + } + lpc->psi = PNV_PSI(obj); } static void pnv_lpc_class_init(ObjectClass *klass, void *data) diff --git a/include/hw/ppc/pnv_lpc.h b/include/hw/ppc/pnv_lpc.h index 38e5506975aa..53040026c37b 100644 --- a/include/hw/ppc/pnv_lpc.h +++ b/include/hw/ppc/pnv_lpc.h @@ -23,6 +23,8 @@ #define PNV_LPC(obj) \ OBJECT_CHECK(PnvLpcController, (obj), TYPE_PNV_LPC) +typedef struct PnvPsi PnvPsi; + typedef struct PnvLpcController { DeviceState parent; @@ -62,6 +64,13 @@ typedef struct PnvLpcController { /* XSCOM registers */ MemoryRegion xscom_regs; + + /* PSI to generate interrupts */ + PnvPsi *psi; } PnvLpcController; +#define LPC_HC_IRQ_SERIRQ0 0x80000000 /* all bits down to ... */ + +void pnv_lpc_eval_irqs(PnvLpcController *lpc); + #endif /* _PPC_PNV_LPC_H */