From patchwork Thu Feb 2 14:34:59 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kirill Batuzov X-Patchwork-Id: 723085 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3vDjkl3mg4z9s7G for ; Fri, 3 Feb 2017 01:56:47 +1100 (AEDT) Received: from localhost ([::1]:57080 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cZIoX-0008UN-2b for incoming@patchwork.ozlabs.org; Thu, 02 Feb 2017 09:56:45 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:35356) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cZIU4-0005NW-DP for qemu-devel@nongnu.org; Thu, 02 Feb 2017 09:35:38 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1cZIU0-0005SJ-VX for qemu-devel@nongnu.org; Thu, 02 Feb 2017 09:35:36 -0500 Received: from bran.ispras.ru ([83.149.199.196]:39804 helo=smtp.ispras.ru) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cZIU0-0005Ow-H0 for qemu-devel@nongnu.org; Thu, 02 Feb 2017 09:35:32 -0500 Received: from bulbul.intra.ispras.ru (spartak.intra.ispras.ru [10.10.3.51]) by smtp.ispras.ru (Postfix) with ESMTP id E8C016178F; Thu, 2 Feb 2017 17:35:31 +0300 (MSK) From: Kirill Batuzov To: qemu-devel@nongnu.org Date: Thu, 2 Feb 2017 17:34:59 +0300 Message-Id: <1486046099-17726-22-git-send-email-batuzovk@ispras.ru> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1486046099-17726-1-git-send-email-batuzovk@ispras.ru> References: <1486046099-17726-1-git-send-email-batuzovk@ispras.ru> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 83.149.199.196 Subject: [Qemu-devel] [PATCH v2.1 21/21] tcg/README: update README to include information about vector opcodes X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Peter Crosthwaite , Kirill Batuzov , Paolo Bonzini , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Richard Henderson Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Kirill Batuzov --- tcg/README | 47 ++++++++++++++++++++++++++++++++++++++++++----- 1 file changed, 42 insertions(+), 5 deletions(-) diff --git a/tcg/README b/tcg/README index a9858c2..209dbc4 100644 --- a/tcg/README +++ b/tcg/README @@ -53,9 +53,18 @@ an "undefined result". TCG instructions operate on variables which are temporaries, local temporaries or globals. TCG instructions and variables are strongly -typed. Two types are supported: 32 bit integers and 64 bit -integers. Pointers are defined as an alias to 32 bit or 64 bit -integers depending on the TCG target word size. +typed. Several types are supported: + +* 32 bit integers, + +* 64 bit integers, + +* 64 bit vectors, + +* 128 bit vectors. + +Pointers are defined as an alias to 32 bit or 64 bit integers +depending on the TCG target word size. Each instruction has a fixed number of output variable operands, input variable operands and always constant operands. @@ -208,6 +217,22 @@ t0=t1%t2 (signed). Undefined behavior if division by zero or overflow. t0=t1%t2 (unsigned). Undefined behavior if division by zero. +* add_i8x16 t0, t1, t2 +add_i16x8 t0, t1, t2 +add_i32x4 t0, t1, t2 +add_i64x2 t0, t1, t2 + +t0=t1+t2 where t0, t1 and t2 are 128 bit vectors of 8, 16, 32 or 64 bit +integers. + +* add_i8x8 t0, t1, t2 +add_i16x4 t0, t1, t2 +add_i32x2 t0, t1, t2 +add_i64x1 t0, t1, t2 + +t0=t1+t2 where t0, t1 and t2 are 64 bit vectors of 8, 16, 32 or 64 bit +integers. + ********* Logical * and_i32/i64 t0, t1, t2 @@ -477,8 +502,8 @@ current TB was linked to this TB. Otherwise execute the next instructions. Only indices 0 and 1 are valid and tcg_gen_goto_tb may be issued at most once with each slot index per TB. -* qemu_ld_i32/i64 t0, t1, flags, memidx -* qemu_st_i32/i64 t0, t1, flags, memidx +* qemu_ld_i32/i64/v128 t0, t1, flags, memidx +* qemu_st_i32/i64/v128 t0, t1, flags, memidx Load data at the guest address t1 into t0, or store data in t0 at guest address t1. The _i32/_i64 size applies to the size of the input/output @@ -488,6 +513,9 @@ and the width of the memory operation is controlled by flags. Both t0 and t1 may be split into little-endian ordered pairs of registers if dealing with 64-bit quantities on a 32-bit host. +The _v128 size can only be used to read exactly 128 bit. Host and target +are required to be of the same endianness for it to work. + The memidx selects the qemu tlb index to use (e.g. user or kernel access). The flags are the TCGMemOp bits, selecting the sign, width, and endianness of the memory access. @@ -538,6 +566,15 @@ Floating point operations are not supported in this version. A previous incarnation of the code generator had full support of them, but it is better to concentrate on integer operations first. +To support vector operations, the backend must define: +- TCG_TARGET_HAS_REGV64 for the 64 bit vector type and/or +- TCG_TARGET_HAS_REG128 for the 128 bit vector type. +For supported types, load and store operations must be supported. An +arbitrary set of other vector operations may be supported. Vector operations +that were not explicitly declared as supported (by defining +TCG_TARGET_HAS_ to 1) will never appear in the intermediate +representation. In this case, the emulation code will be emitted instead. + 4.2) Constraints GCC like constraints are used to define the constraints of every