From patchwork Thu Feb 2 14:34:55 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kirill Batuzov X-Patchwork-Id: 723046 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3vDjJD1Wgjz9s7N for ; Fri, 3 Feb 2017 01:37:16 +1100 (AEDT) Received: from localhost ([::1]:56988 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cZIVd-0006nQ-GV for incoming@patchwork.ozlabs.org; Thu, 02 Feb 2017 09:37:13 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:35294) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cZIU3-0005MK-67 for qemu-devel@nongnu.org; Thu, 02 Feb 2017 09:35:37 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1cZITz-0005RF-Os for qemu-devel@nongnu.org; Thu, 02 Feb 2017 09:35:35 -0500 Received: from bran.ispras.ru ([83.149.199.196]:39804 helo=smtp.ispras.ru) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cZITz-0005Ow-BT for qemu-devel@nongnu.org; Thu, 02 Feb 2017 09:35:31 -0500 Received: from bulbul.intra.ispras.ru (spartak.intra.ispras.ru [10.10.3.51]) by smtp.ispras.ru (Postfix) with ESMTP id C7DA36178B; Thu, 2 Feb 2017 17:35:30 +0300 (MSK) From: Kirill Batuzov To: qemu-devel@nongnu.org Date: Thu, 2 Feb 2017 17:34:55 +0300 Message-Id: <1486046099-17726-18-git-send-email-batuzovk@ispras.ru> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1486046099-17726-1-git-send-email-batuzovk@ispras.ru> References: <1486046099-17726-1-git-send-email-batuzovk@ispras.ru> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 83.149.199.196 Subject: [Qemu-devel] [PATCH v2.1 17/21] tcg: introduce qemu_ld_v128 and qemu_st_v128 opcodes X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Peter Crosthwaite , Kirill Batuzov , Paolo Bonzini , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Richard Henderson Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Kirill Batuzov --- tcg/i386/tcg-target.inc.c | 5 +++++ tcg/tcg-op.c | 24 ++++++++++++++++++++++++ tcg/tcg-op.h | 15 +++++++++++++++ tcg/tcg-opc.h | 4 ++++ 4 files changed, 48 insertions(+) diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c index 263c15e..1e6edc0 100644 --- a/tcg/i386/tcg-target.inc.c +++ b/tcg/i386/tcg-target.inc.c @@ -2448,6 +2448,7 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) = { .args_ct_str = { "L", "L", "L", "L" } }; static const TCGTargetOpDef V_r = { .args_ct_str = { "V", "r" } }; static const TCGTargetOpDef V_0_V = { .args_ct_str = { "V", "0", "V" } }; + static const TCGTargetOpDef V_L = { .args_ct_str = { "V", "L" } }; switch (op) { case INDEX_op_ld8u_i32: @@ -2662,6 +2663,10 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) case INDEX_op_add_i64x1: return &V_0_V; + case INDEX_op_qemu_ld_v128: + case INDEX_op_qemu_st_v128: + return &V_L; + default: break; } diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index 0dfe611..db74017 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -3102,3 +3102,27 @@ void tcg_v64_to_ptr(TCGv_v64 tmp, TCGv_ptr base, int slot, } } } + +void tcg_gen_qemu_ld_v128(TCGv_v128 val, TCGv addr, TCGArg idx, + TCGMemOp memop) +{ +#ifdef TCG_TARGET_HAS_REG128 + tcg_debug_assert((memop & MO_BSWAP) == MO_TE); + TCGMemOpIdx oi = make_memop_idx(memop, idx); + tcg_gen_op3si_v128(INDEX_op_qemu_ld_v128, val, addr, oi); +#else + g_assert_not_reached(); +#endif +} + +void tcg_gen_qemu_st_v128(TCGv_v128 val, TCGv addr, TCGArg idx, + TCGMemOp memop) +{ +#ifdef TCG_TARGET_HAS_REG128 + tcg_debug_assert((memop & MO_BSWAP) == MO_TE); + TCGMemOpIdx oi = make_memop_idx(memop, idx); + tcg_gen_op3si_v128(INDEX_op_qemu_st_v128, val, addr, oi); +#else + g_assert_not_reached(); +#endif +} diff --git a/tcg/tcg-op.h b/tcg/tcg-op.h index 3727be7..dc1d032 100644 --- a/tcg/tcg-op.h +++ b/tcg/tcg-op.h @@ -266,6 +266,19 @@ static inline void tcg_gen_op3_v128(TCGOpcode opc, TCGv_v128 a1, GET_TCGV_V128(a3)); } +static inline void tcg_gen_op3si_v128(TCGOpcode opc, TCGv_v128 a1, + TCGv a2, TCGArg a3) +{ +#if TARGET_LONG_BITS == 64 && TCG_TARGET_REG_BITS == 32 + tcg_gen_op4(&tcg_ctx, opc, GET_TCGV_V128(a1), GET_TCGV_I32(TCGV_LOW(a2)), + GET_TCGV_I32(TCGV_HIGH(a2)), a3); +#elif TARGET_LONG_BITS == 32 + tcg_gen_op3(&tcg_ctx, opc, GET_TCGV_V128(a1), GET_TCGV_I32(a2), a3); +#else + tcg_gen_op3(&tcg_ctx, opc, GET_TCGV_V128(a1), GET_TCGV_I64(a2), a3); +#endif +} + static inline void tcg_gen_op1_v64(TCGOpcode opc, TCGv_v64 a1) { tcg_gen_op1(&tcg_ctx, opc, GET_TCGV_V64(a1)); @@ -909,6 +922,8 @@ void tcg_gen_qemu_ld_i32(TCGv_i32, TCGv, TCGArg, TCGMemOp); void tcg_gen_qemu_st_i32(TCGv_i32, TCGv, TCGArg, TCGMemOp); void tcg_gen_qemu_ld_i64(TCGv_i64, TCGv, TCGArg, TCGMemOp); void tcg_gen_qemu_st_i64(TCGv_i64, TCGv, TCGArg, TCGMemOp); +void tcg_gen_qemu_ld_v128(TCGv_v128, TCGv, TCGArg, TCGMemOp); +void tcg_gen_qemu_st_v128(TCGv_v128, TCGv, TCGArg, TCGMemOp); static inline void tcg_gen_qemu_ld8u(TCGv ret, TCGv addr, int mem_index) { diff --git a/tcg/tcg-opc.h b/tcg/tcg-opc.h index 4c8f195..6c2e697 100644 --- a/tcg/tcg-opc.h +++ b/tcg/tcg-opc.h @@ -232,6 +232,10 @@ DEF(qemu_ld_i64, DATA64_ARGS, TLADDR_ARGS, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS | TCG_OPF_64BIT) DEF(qemu_st_i64, 0, TLADDR_ARGS + DATA64_ARGS, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS | TCG_OPF_64BIT) +DEF(qemu_ld_v128, 1, 1, 1, + TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS | IMPL128) +DEF(qemu_st_v128, 0, 2, 1, + TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS | IMPL128) #undef TLADDR_ARGS #undef DATA64_ARGS