From patchwork Thu Feb 2 14:34:50 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kirill Batuzov X-Patchwork-Id: 723069 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3vDjZ41HWGz9s7K for ; Fri, 3 Feb 2017 01:49:16 +1100 (AEDT) Received: from localhost ([::1]:57044 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cZIhF-0001Mu-Lg for incoming@patchwork.ozlabs.org; Thu, 02 Feb 2017 09:49:13 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:35280) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cZIU2-0005M6-RJ for qemu-devel@nongnu.org; Thu, 02 Feb 2017 09:35:40 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1cZITy-0005Q6-7G for qemu-devel@nongnu.org; Thu, 02 Feb 2017 09:35:34 -0500 Received: from bran.ispras.ru ([83.149.199.196]:39800 helo=smtp.ispras.ru) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cZITy-0005OW-0L for qemu-devel@nongnu.org; Thu, 02 Feb 2017 09:35:30 -0500 Received: from bulbul.intra.ispras.ru (spartak.intra.ispras.ru [10.10.3.51]) by smtp.ispras.ru (Postfix) with ESMTP id 6DC5D612F1; Thu, 2 Feb 2017 17:35:29 +0300 (MSK) From: Kirill Batuzov To: qemu-devel@nongnu.org Date: Thu, 2 Feb 2017 17:34:50 +0300 Message-Id: <1486046099-17726-13-git-send-email-batuzovk@ispras.ru> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1486046099-17726-1-git-send-email-batuzovk@ispras.ru> References: <1486046099-17726-1-git-send-email-batuzovk@ispras.ru> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 83.149.199.196 Subject: [Qemu-devel] [PATCH v2.1 12/21] tcg/i386: support 64-bit vector operations X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Peter Crosthwaite , Kirill Batuzov , Paolo Bonzini , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Richard Henderson Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Kirill Batuzov --- tcg/i386/tcg-target.h | 1 + tcg/i386/tcg-target.inc.c | 22 ++++++++++++++++++++++ 2 files changed, 23 insertions(+) diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h index b0704e8..755ebaa 100644 --- a/tcg/i386/tcg-target.h +++ b/tcg/i386/tcg-target.h @@ -31,6 +31,7 @@ #ifdef __x86_64__ # if defined(TARGET_WORDS_BIGENDIAN) == defined(HOST_WORDS_BIGENDIAN) # define TCG_TARGET_HAS_REG128 1 +# define TCG_TARGET_HAS_REGV64 1 # endif # ifdef TCG_TARGET_HAS_REG128 # define TCG_TARGET_REG_BITS 64 diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c index 3e718f3..208bb81 100644 --- a/tcg/i386/tcg-target.inc.c +++ b/tcg/i386/tcg-target.inc.c @@ -390,6 +390,9 @@ static inline int tcg_target_const_match(tcg_target_long val, TCGType type, #define OPC_MOVDQU_M2R (0x6f | P_SSE_F30F) /* store 128-bit value */ #define OPC_MOVDQU_R2M (0x7f | P_SSE_F30F) /* load 128-bit value */ #define OPC_MOVDQA_R2R (0x6f | P_SSE_660F) /* reg-to-reg 128-bit mov */ +#define OPC_MOVQ_M2R (0x7e | P_SSE_F30F) +#define OPC_MOVQ_R2M (0xd6 | P_SSE_660F) +#define OPC_MOVQ_R2R (0x7e | P_SSE_F30F) #define OPC_PADDD (0xfe | P_SSE_660F) /* Group 1 opcode extensions for 0x80-0x83. @@ -700,6 +703,15 @@ static inline void tcg_out_mov(TCGContext *s, TCGType type, tcg_out_modrm(s, OPC_MOVDQA_R2R, ret, arg); } break; + case TCG_TYPE_V64: + ret -= TCG_REG_XMM0; + arg -= TCG_REG_XMM0; + if (have_avx) { + tcg_out_vex_modrm(s, OPC_MOVQ_R2R, ret, 15, arg); + } else { + tcg_out_modrm(s, OPC_MOVQ_R2R, ret, arg); + } + break; case TCG_TYPE_I32: case TCG_TYPE_I64: opc = OPC_MOVL_GvEv + (type == TCG_TYPE_I64 ? P_REXW : 0); @@ -788,6 +800,10 @@ static inline void tcg_out_ld(TCGContext *s, TCGType type, TCGReg ret, ret -= TCG_REG_XMM0; tcg_out_modrm_offset(s, OPC_MOVDQU_M2R, ret, arg1, arg2); break; + case TCG_TYPE_V64: + ret -= TCG_REG_XMM0; + tcg_out_modrm_offset(s, OPC_MOVQ_M2R, ret, arg1, arg2); + break; case TCG_TYPE_I32: case TCG_TYPE_I64: opc = OPC_MOVL_GvEv + (type == TCG_TYPE_I64 ? P_REXW : 0); @@ -807,6 +823,10 @@ static inline void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg, arg -= TCG_REG_XMM0; tcg_out_modrm_offset(s, OPC_MOVDQU_R2M, arg, arg1, arg2); break; + case TCG_TYPE_V64: + arg -= TCG_REG_XMM0; + tcg_out_modrm_offset(s, OPC_MOVQ_R2M, arg, arg1, arg2); + break; case TCG_TYPE_I32: case TCG_TYPE_I64: opc = OPC_MOVL_EvGv + (type == TCG_TYPE_I64 ? P_REXW : 0); @@ -2407,6 +2427,8 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) case INDEX_op_ld_v128: case INDEX_op_st_v128: + case INDEX_op_ld_v64: + case INDEX_op_st_v64: return &V_r; case INDEX_op_st8_i32: