From patchwork Wed Feb 1 12:18:06 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kirill Batuzov X-Patchwork-Id: 722501 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3vD2yX25y8z9sxS for ; Wed, 1 Feb 2017 23:49:40 +1100 (AEDT) Received: from localhost ([::1]:50405 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cYuLx-0002BM-KC for incoming@patchwork.ozlabs.org; Wed, 01 Feb 2017 07:49:37 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:53140) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cYtsA-00060D-TY for qemu-devel@nongnu.org; Wed, 01 Feb 2017 07:18:52 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1cYts6-0005c9-6V for qemu-devel@nongnu.org; Wed, 01 Feb 2017 07:18:50 -0500 Received: from bran.ispras.ru ([83.149.199.196]:46077 helo=smtp.ispras.ru) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cYts5-0005bg-W6 for qemu-devel@nongnu.org; Wed, 01 Feb 2017 07:18:46 -0500 Received: from bulbul.intra.ispras.ru (spartak.intra.ispras.ru [10.10.3.51]) by smtp.ispras.ru (Postfix) with ESMTP id 27611612F0; Wed, 1 Feb 2017 15:18:45 +0300 (MSK) From: Kirill Batuzov To: qemu-devel@nongnu.org Date: Wed, 1 Feb 2017 15:18:06 +0300 Message-Id: <1485951502-28774-5-git-send-email-batuzovk@ispras.ru> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1485951502-28774-1-git-send-email-batuzovk@ispras.ru> References: <1485951502-28774-1-git-send-email-batuzovk@ispras.ru> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 83.149.199.196 Subject: [Qemu-devel] [PATCH v2 04/20] tcg: add ld_v128, ld_v64, st_v128 and st_v64 opcodes X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Peter Crosthwaite , Kirill Batuzov , Paolo Bonzini , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Richard Henderson Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Kirill Batuzov --- tcg/tcg-op.h | 38 ++++++++++++++++++++++++++++++++++++++ tcg/tcg-opc.h | 18 ++++++++++++++++++ 2 files changed, 56 insertions(+) diff --git a/tcg/tcg-op.h b/tcg/tcg-op.h index 517745e..250493b 100644 --- a/tcg/tcg-op.h +++ b/tcg/tcg-op.h @@ -501,6 +501,44 @@ static inline void tcg_gen_discard_v64(TCGv_v64 arg) tcg_gen_op1_v64(INDEX_op_discard, arg); } +static inline void tcg_gen_ldst_op_v128(TCGOpcode opc, TCGv_v128 val, + TCGv_ptr base, TCGArg offset) +{ + tcg_gen_op3(&tcg_ctx, opc, GET_TCGV_V128(val), GET_TCGV_PTR(base), + offset); +} + +static inline void tcg_gen_st_v128(TCGv_v128 arg1, TCGv_ptr arg2, + tcg_target_long offset) +{ + tcg_gen_ldst_op_v128(INDEX_op_st_v128, arg1, arg2, offset); +} + +static inline void tcg_gen_ld_v128(TCGv_v128 ret, TCGv_ptr arg2, + tcg_target_long offset) +{ + tcg_gen_ldst_op_v128(INDEX_op_ld_v128, ret, arg2, offset); +} + +static inline void tcg_gen_ldst_op_v64(TCGOpcode opc, TCGv_v64 val, + TCGv_ptr base, TCGArg offset) +{ + tcg_gen_op3(&tcg_ctx, opc, GET_TCGV_V64(val), GET_TCGV_PTR(base), + offset); +} + +static inline void tcg_gen_st_v64(TCGv_v64 arg1, TCGv_ptr arg2, + tcg_target_long offset) +{ + tcg_gen_ldst_op_v64(INDEX_op_st_v64, arg1, arg2, offset); +} + +static inline void tcg_gen_ld_v64(TCGv_v64 ret, TCGv_ptr arg2, + tcg_target_long offset) +{ + tcg_gen_ldst_op_v64(INDEX_op_ld_v64, ret, arg2, offset); +} + /* 64 bit ops */ void tcg_gen_addi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2); diff --git a/tcg/tcg-opc.h b/tcg/tcg-opc.h index f06f894..2365c97 100644 --- a/tcg/tcg-opc.h +++ b/tcg/tcg-opc.h @@ -42,6 +42,18 @@ DEF(br, 0, 0, 1, TCG_OPF_BB_END) # define IMPL64 TCG_OPF_64BIT #endif +#ifdef TCG_TARGET_HAS_REG128 +# define IMPL128 0 +#else +# define IMPL128 TCG_OPF_NOT_PRESENT +#endif + +#ifdef TCG_TARGET_HAS_REGV64 +# define IMPLV64 0 +#else +# define IMPLV64 TCG_OPF_NOT_PRESENT +#endif + DEF(mb, 0, 0, 1, 0) DEF(mov_i32, 1, 1, 0, TCG_OPF_NOT_PRESENT) @@ -188,6 +200,12 @@ DEF(mulsh_i64, 1, 2, 0, IMPL(TCG_TARGET_HAS_mulsh_i64)) #define TLADDR_ARGS (TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? 1 : 2) #define DATA64_ARGS (TCG_TARGET_REG_BITS == 64 ? 1 : 2) +/* load/store */ +DEF(st_v128, 0, 2, 1, IMPL128) +DEF(ld_v128, 1, 1, 1, IMPL128) +DEF(st_v64, 0, 2, 1, IMPLV64) +DEF(ld_v64, 1, 1, 1, IMPLV64) + /* QEMU specific */ DEF(insn_start, 0, 0, TLADDR_ARGS * TARGET_INSN_START_WORDS, TCG_OPF_NOT_PRESENT)