@@ -2448,6 +2448,7 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
= { .args_ct_str = { "L", "L", "L", "L" } };
static const TCGTargetOpDef V_r = { .args_ct_str = { "V", "r" } };
static const TCGTargetOpDef V_0_V = { .args_ct_str = { "V", "0", "V" } };
+ static const TCGTargetOpDef V_L = { .args_ct_str = { "V", "L" } };
switch (op) {
case INDEX_op_ld8u_i32:
@@ -2662,6 +2663,10 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
case INDEX_op_add_i64x1:
return &V_0_V;
+ case INDEX_op_qemu_ld_v128:
+ case INDEX_op_qemu_st_v128:
+ return &V_L;
+
default:
break;
}
@@ -3102,3 +3102,27 @@ void tcg_v64_to_ptr(TCGv_v64 tmp, TCGv_ptr base, int slot,
}
}
}
+
+void tcg_gen_qemu_ld_v128(TCGv_v128 val, TCGv addr, TCGArg idx,
+ TCGMemOp memop)
+{
+#ifdef TCG_TARGET_HAS_REG128
+ tcg_debug_assert((memop & MO_BSWAP) == MO_TE);
+ TCGMemOpIdx oi = make_memop_idx(memop, idx);
+ tcg_gen_op3si_v128(INDEX_op_qemu_ld_v128, val, addr, oi);
+#else
+ g_assert_not_reached();
+#endif
+}
+
+void tcg_gen_qemu_st_v128(TCGv_v128 val, TCGv addr, TCGArg idx,
+ TCGMemOp memop)
+{
+#ifdef TCG_TARGET_HAS_REG128
+ tcg_debug_assert((memop & MO_BSWAP) == MO_TE);
+ TCGMemOpIdx oi = make_memop_idx(memop, idx);
+ tcg_gen_op3si_v128(INDEX_op_qemu_st_v128, val, addr, oi);
+#else
+ g_assert_not_reached();
+#endif
+}
@@ -266,6 +266,19 @@ static inline void tcg_gen_op3_v128(TCGOpcode opc, TCGv_v128 a1,
GET_TCGV_V128(a3));
}
+static inline void tcg_gen_op3si_v128(TCGOpcode opc, TCGv_v128 a1,
+ TCGv a2, TCGArg a3)
+{
+#if TARGET_LONG_BITS == 64 && TCG_TARGET_REG_BITS == 32
+ tcg_gen_op4(&tcg_ctx, opc, GET_TCGV_V128(a1), GET_TCGV_I32(TCGV_LOW(a2)),
+ GET_TCGV_I32(TCGV_HIGH(a2)), a3);
+#elif TARGET_LONG_BITS == 32
+ tcg_gen_op3(&tcg_ctx, opc, GET_TCGV_V128(a1), GET_TCGV_I32(a2), a3);
+#else
+ tcg_gen_op3(&tcg_ctx, opc, GET_TCGV_V128(a1), GET_TCGV_I64(a2), a3);
+#endif
+}
+
static inline void tcg_gen_op1_v64(TCGOpcode opc, TCGv_v64 a1)
{
tcg_gen_op1(&tcg_ctx, opc, GET_TCGV_V64(a1));
@@ -909,6 +922,8 @@ void tcg_gen_qemu_ld_i32(TCGv_i32, TCGv, TCGArg, TCGMemOp);
void tcg_gen_qemu_st_i32(TCGv_i32, TCGv, TCGArg, TCGMemOp);
void tcg_gen_qemu_ld_i64(TCGv_i64, TCGv, TCGArg, TCGMemOp);
void tcg_gen_qemu_st_i64(TCGv_i64, TCGv, TCGArg, TCGMemOp);
+void tcg_gen_qemu_ld_v128(TCGv_v128, TCGv, TCGArg, TCGMemOp);
+void tcg_gen_qemu_st_v128(TCGv_v128, TCGv, TCGArg, TCGMemOp);
static inline void tcg_gen_qemu_ld8u(TCGv ret, TCGv addr, int mem_index)
{
@@ -232,6 +232,10 @@ DEF(qemu_ld_i64, DATA64_ARGS, TLADDR_ARGS, 1,
TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS | TCG_OPF_64BIT)
DEF(qemu_st_i64, 0, TLADDR_ARGS + DATA64_ARGS, 1,
TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS | TCG_OPF_64BIT)
+DEF(qemu_ld_v128, 1, 1, 1,
+ TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS | IMPL128)
+DEF(qemu_st_v128, 0, 2, 1,
+ TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS | IMPL128)
#undef TLADDR_ARGS
#undef DATA64_ARGS
Signed-off-by: Kirill Batuzov <batuzovk@ispras.ru> --- tcg/i386/tcg-target.inc.c | 5 +++++ tcg/tcg-op.c | 24 ++++++++++++++++++++++++ tcg/tcg-op.h | 15 +++++++++++++++ tcg/tcg-opc.h | 4 ++++ 4 files changed, 48 insertions(+)