From patchwork Tue Jan 17 09:07:48 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kirill Batuzov X-Patchwork-Id: 716071 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3v2kny04dDz9srY for ; Tue, 17 Jan 2017 20:09:58 +1100 (AEDT) Received: from localhost ([::1]:33679 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cTPm7-0004Mv-FJ for incoming@patchwork.ozlabs.org; Tue, 17 Jan 2017 04:09:55 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:50925) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cTPkh-00039i-5M for qemu-devel@nongnu.org; Tue, 17 Jan 2017 04:08:30 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1cTPkg-0003tu-5E for qemu-devel@nongnu.org; Tue, 17 Jan 2017 04:08:27 -0500 Received: from bran.ispras.ru ([83.149.199.196]:50116 helo=smtp.ispras.ru) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cTPkf-0003sL-NF for qemu-devel@nongnu.org; Tue, 17 Jan 2017 04:08:26 -0500 Received: from bulbul.intra.ispras.ru (spartak.intra.ispras.ru [10.10.3.51]) by smtp.ispras.ru (Postfix) with ESMTP id A95A6612D1; Tue, 17 Jan 2017 12:08:24 +0300 (MSK) From: Kirill Batuzov To: qemu-devel@nongnu.org Date: Tue, 17 Jan 2017 12:07:48 +0300 Message-Id: <1484644078-21312-9-git-send-email-batuzovk@ispras.ru> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1484644078-21312-1-git-send-email-batuzovk@ispras.ru> References: <1484644078-21312-1-git-send-email-batuzovk@ispras.ru> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 83.149.199.196 Subject: [Qemu-devel] [PATCH 08/18] target/arm: support access to vector guest registers as globals X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Peter Crosthwaite , Kirill Batuzov , Paolo Bonzini , Richard Henderson Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" To support vector guest registers as globals we need to do two things: 1) create corresponding globals, 2) mark which globals can overlap, Signed-off-by: Kirill Batuzov --- I've declared regnames for new globals the same way they used to be declared for scalar regs. checkpatch complains about it. Should I move '{' to the same line for all 3 arrays? --- target/arm/translate.c | 45 +++++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 43 insertions(+), 2 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 0ad9070..2b81b5d 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -65,6 +65,12 @@ static TCGv_i32 cpu_R[16]; TCGv_i32 cpu_CF, cpu_NF, cpu_VF, cpu_ZF; TCGv_i64 cpu_exclusive_addr; TCGv_i64 cpu_exclusive_val; +static TCGv_v128 cpu_Q[16]; +static TCGv_v64 cpu_D[32]; +#ifdef CONFIG_USER_ONLY +TCGv_i64 cpu_exclusive_test; +TCGv_i32 cpu_exclusive_info; +#endif /* FIXME: These should be removed. */ static TCGv_i32 cpu_F0s, cpu_F1s; @@ -72,14 +78,26 @@ static TCGv_i64 cpu_F0d, cpu_F1d; #include "exec/gen-icount.h" -static const char *regnames[] = +static const char *regnames_r[] = { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "r13", "r14", "pc" }; +static const char *regnames_q[] = + { "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7", + "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15" }; + +static const char *regnames_d[] = + { "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", + "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15", + "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23", + "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31" }; + /* initialize TCG globals. */ void arm_translate_init(void) { int i; + static TCGArg overlap_temps[16][2]; + static TCGArg sub_temps[16][3]; cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env"); tcg_ctx.tcg_env = cpu_env; @@ -87,7 +105,30 @@ void arm_translate_init(void) for (i = 0; i < 16; i++) { cpu_R[i] = tcg_global_mem_new_i32(cpu_env, offsetof(CPUARMState, regs[i]), - regnames[i]); + regnames_r[i]); + } + for (i = 0; i < 16; i++) { + cpu_Q[i] = tcg_global_mem_new_v128(cpu_env, + offsetof(CPUARMState, + vfp.regs[2 * i]), + regnames_q[i]); + } + for (i = 0; i < 32; i++) { + cpu_D[i] = tcg_global_mem_new_v64(cpu_env, + offsetof(CPUARMState, vfp.regs[i]), + regnames_d[i]); + } + for (i = 0; i < 16; i++) { + overlap_temps[i][0] = GET_TCGV_V128(cpu_Q[i]); + overlap_temps[i][1] = (TCGArg)-1; + sub_temps[i][0] = GET_TCGV_V64(cpu_D[i * 2]); + sub_temps[i][1] = GET_TCGV_V64(cpu_D[i * 2 + 1]); + sub_temps[i][2] = (TCGArg)-1; + tcg_temp_set_overlap_temps(GET_TCGV_V64(cpu_D[i * 2]), + overlap_temps[i]); + tcg_temp_set_overlap_temps(GET_TCGV_V64(cpu_D[i * 2 + 1]), + overlap_temps[i]); + tcg_temp_set_sub_temps(GET_TCGV_V128(cpu_Q[i]), sub_temps[i]); } cpu_CF = tcg_global_mem_new_i32(cpu_env, offsetof(CPUARMState, CF), "CF"); cpu_NF = tcg_global_mem_new_i32(cpu_env, offsetof(CPUARMState, NF), "NF");