From patchwork Tue Jan 17 09:07:58 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kirill Batuzov X-Patchwork-Id: 716100 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3v2lYz3LHJz9tJD for ; Tue, 17 Jan 2017 20:44:39 +1100 (AEDT) Received: from localhost ([::1]:33882 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cTQJh-0005W1-44 for incoming@patchwork.ozlabs.org; Tue, 17 Jan 2017 04:44:37 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:51046) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cTPkp-0003Ha-DA for qemu-devel@nongnu.org; Tue, 17 Jan 2017 04:08:39 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1cTPko-0003z5-IB for qemu-devel@nongnu.org; Tue, 17 Jan 2017 04:08:35 -0500 Received: from bran.ispras.ru ([83.149.199.196]:50408 helo=smtp.ispras.ru) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cTPko-0003yh-AO for qemu-devel@nongnu.org; Tue, 17 Jan 2017 04:08:34 -0500 Received: from bulbul.intra.ispras.ru (spartak.intra.ispras.ru [10.10.3.51]) by smtp.ispras.ru (Postfix) with ESMTP id 2D8B361789; Tue, 17 Jan 2017 12:08:33 +0300 (MSK) From: Kirill Batuzov To: qemu-devel@nongnu.org Date: Tue, 17 Jan 2017 12:07:58 +0300 Message-Id: <1484644078-21312-19-git-send-email-batuzovk@ispras.ru> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1484644078-21312-1-git-send-email-batuzovk@ispras.ru> References: <1484644078-21312-1-git-send-email-batuzovk@ispras.ru> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 83.149.199.196 Subject: [Qemu-devel] [PATCH 18/18] target/arm: load two consecutive 64-bits vector regs as a 128-bit vector reg X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Peter Crosthwaite , Kirill Batuzov , Paolo Bonzini , Richard Henderson Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" ARM instruction set does not have loads to 128-bit vector register (q-regs). Instead it can read several consecutive 64-bit vector register (d-regs) which is used by GCC to load 128-bit registers from memory. For vector operations to work we need to detect such loads and transform them into 128-bit loads to 128-bit temporaries. Signed-off-by: Kirill Batuzov --- target/arm/translate.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/target/arm/translate.c b/target/arm/translate.c index 4378d44..8b28f77 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -4748,6 +4748,19 @@ static int disas_neon_ls_insn(DisasContext *s, uint32_t insn) tcg_gen_addi_i32(addr, addr, 1 << size); } if (size == 3) { +#ifdef TCG_TARGET_HAS_REG128 + if (rd % 2 == 0 && nregs == 2) { + /* 128-bit load */ + if (load) { + tcg_gen_qemu_ld_v128(cpu_Q[rd / 2], addr, + get_mem_index(s), MO_LE | MO_128); + } else { + tcg_gen_qemu_st_v128(cpu_Q[rd / 2], addr, + get_mem_index(s), MO_LE | MO_128); + } + break; + } +#endif tmp64 = tcg_temp_new_i64(); if (load) { gen_aa32_ld64(s, tmp64, addr, get_mem_index(s));