From patchwork Tue Dec 27 17:53:57 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Laurent Vivier X-Patchwork-Id: 709085 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3tp3k94Hyxz9t0w for ; Wed, 28 Dec 2016 05:07:45 +1100 (AEDT) Received: from localhost ([::1]:55323 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cLwA3-00028h-9z for incoming@patchwork.ozlabs.org; Tue, 27 Dec 2016 13:07:43 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:37519) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cLvxH-0000Iu-US for qemu-devel@nongnu.org; Tue, 27 Dec 2016 12:54:36 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1cLvxD-0000OR-LT for qemu-devel@nongnu.org; Tue, 27 Dec 2016 12:54:32 -0500 Received: from mout.kundenserver.de ([212.227.126.187]:59527) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1cLvxD-0000OB-9P for qemu-devel@nongnu.org; Tue, 27 Dec 2016 12:54:27 -0500 Received: from Quad.localdomain ([78.238.229.36]) by mrelayeu.kundenserver.de (mreue001 [212.227.15.167]) with ESMTPSA (Nemesis) id 0McvNR-1c4gBF3CoD-00Hy8R; Tue, 27 Dec 2016 18:54:09 +0100 From: Laurent Vivier To: qemu-devel@nongnu.org Date: Tue, 27 Dec 2016 18:53:57 +0100 Message-Id: <1482861241-17678-9-git-send-email-laurent@vivier.eu> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1482861241-17678-1-git-send-email-laurent@vivier.eu> References: <1482861241-17678-1-git-send-email-laurent@vivier.eu> X-Provags-ID: V03:K0:NDiRG+ERLH4+2wpa+jg2m9tgM8FMnVeRMZ9oDasmQop6venVI3f 0AKedV5nxs81XBFa5e3Ow0Eoyf8q1FB9dUaopC8WhCS7TeQsT98kRNiwaAdo+otZmKGJQ9D tLaPT4QkSQaPNf4CkqqAjuJzEkjKQJP9wRlXh1d3Yg12DgUaDeJrMbXJtcVso+POpd1mZZp g5Je9dehg42VYrFgMWJ3g== X-UI-Out-Filterresults: notjunk:1; V01:K0:Cqu0og7o9m0=:/3wUOOIy2smFIMettRHz23 zEnJUHGA37Rjm5uj2b2J3jjNLVf78EqW12btPCRfEoOdsoLeoACo40g/NdtAt8NZs2JlTETV6 0NIN334uX2pf/FV1VPRM9mj1moEpuNzGqqBAHk66C8kS3w0A6b1cNlCjYW6yUhtfoha/oRUWz WRiHbBBWZ2zl5FWG4Uck2ivDQa6SQ0FB8NuIj+3cqobzxzqPR8GdQIBnNzKThTzy+S67DV/tU kuNQW8vdZUgIIQJGLnxVNn6IuWvHyLfCBDRQ4I1Yc5ZxR7Y/KUX7oaOUNxdkUY+sXLiZLzKc/ bTtqbPV7fQ9SQgT6bJAojdERDPnU1S7mjqNg7OlbzLUY2ypoHylToYsWlswjJr0KSCTC5qf6w eNalcuYP4depcSuLwY/e4TyGu+cqoERehmmZd2qUywQQ+g8ntd0e5enHCjqkJGP3UvILTG3QS ccZmpfvlXCpmf9BmNEPqYc/c7WQeDiqYvjHzT2MHQMzloM13kakylHaDpO57hPmGlQrie4DZ6 Uhf8b8VwNxH+qkA99L7bDnDJVSM6hmIUbeibMiRoYEc5KfbEN/4P5L0ZMexsUDzX8OpljBpL5 lzHz8L57O1o4MsL20UN/cWuxz1ARifY80q/sgiS2FTys/5odPZMtIT/kS0tnVdbOtH2CbSEUe WAECpqmMldx/Mdaow7vOyQbCFJNswee54POt2LQdoiKPlFvA3KFDTo+Obcuu+28Naj94= X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 212.227.126.187 Subject: [Qemu-devel] [PULL v2 08/12] target-m68k: Implement 680x0 movem X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Laurent Vivier , Richard Henderson Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" 680x0 movem can load/store words and long words and can use more addressing modes. Coldfire can only use long words with (Ax) and (d16,Ax) addressing modes. Signed-off-by: Laurent Vivier Signed-off-by: Richard Henderson Message-Id: <1478699171-10637-2-git-send-email-rth@twiddle.net> --- target/m68k/translate.c | 130 +++++++++++++++++++++++++++++++++++++++--------- 1 file changed, 107 insertions(+), 23 deletions(-) diff --git a/target/m68k/translate.c b/target/m68k/translate.c index 0124820..acc8182 100644 --- a/target/m68k/translate.c +++ b/target/m68k/translate.c @@ -1645,40 +1645,122 @@ static void gen_push(DisasContext *s, TCGv val) tcg_gen_mov_i32(QREG_SP, tmp); } +static TCGv mreg(int reg) +{ + if (reg < 8) { + /* Dx */ + return cpu_dregs[reg]; + } + /* Ax */ + return cpu_aregs[reg & 7]; +} + DISAS_INSN(movem) { - TCGv addr; + TCGv addr, incr, tmp, r[16]; + int is_load = (insn & 0x0400) != 0; + int opsize = (insn & 0x40) != 0 ? OS_LONG : OS_WORD; + uint16_t mask = read_im16(env, s); + int mode = extract32(insn, 3, 3); + int reg0 = REG(insn, 0); int i; - uint16_t mask; - TCGv reg; - TCGv tmp; - int is_load; - mask = read_im16(env, s); - tmp = gen_lea(env, s, insn, OS_LONG); - if (IS_NULL_QREG(tmp)) { + tmp = cpu_aregs[reg0]; + + switch (mode) { + case 0: /* data register direct */ + case 1: /* addr register direct */ + do_addr_fault: gen_addr_fault(s); return; + + case 2: /* indirect */ + break; + + case 3: /* indirect post-increment */ + if (!is_load) { + /* post-increment is not allowed */ + goto do_addr_fault; + } + break; + + case 4: /* indirect pre-decrement */ + if (is_load) { + /* pre-decrement is not allowed */ + goto do_addr_fault; + } + /* We want a bare copy of the address reg, without any pre-decrement + adjustment, as gen_lea would provide. */ + break; + + default: + tmp = gen_lea_mode(env, s, mode, reg0, opsize); + if (IS_NULL_QREG(tmp)) { + goto do_addr_fault; + } + break; } + addr = tcg_temp_new(); tcg_gen_mov_i32(addr, tmp); - is_load = ((insn & 0x0400) != 0); - for (i = 0; i < 16; i++, mask >>= 1) { - if (mask & 1) { - if (i < 8) - reg = DREG(i, 0); - else - reg = AREG(i, 0); - if (is_load) { - tmp = gen_load(s, OS_LONG, addr, 0); - tcg_gen_mov_i32(reg, tmp); - } else { - gen_store(s, OS_LONG, addr, reg); + incr = tcg_const_i32(opsize_bytes(opsize)); + + if (is_load) { + /* memory to register */ + for (i = 0; i < 16; i++) { + if (mask & (1 << i)) { + r[i] = gen_load(s, opsize, addr, 1); + tcg_gen_add_i32(addr, addr, incr); + } + } + for (i = 0; i < 16; i++) { + if (mask & (1 << i)) { + tcg_gen_mov_i32(mreg(i), r[i]); + tcg_temp_free(r[i]); + } + } + if (mode == 3) { + /* post-increment: movem (An)+,X */ + tcg_gen_mov_i32(cpu_aregs[reg0], addr); + } + } else { + /* register to memory */ + if (mode == 4) { + /* pre-decrement: movem X,-(An) */ + for (i = 15; i >= 0; i--) { + if ((mask << i) & 0x8000) { + tcg_gen_sub_i32(addr, addr, incr); + if (reg0 + 8 == i && + m68k_feature(s->env, M68K_FEATURE_EXT_FULL)) { + /* M68020+: if the addressing register is the + * register moved to memory, the value written + * is the initial value decremented by the size of + * the operation, regardless of how many actual + * stores have been performed until this point. + * M68000/M68010: the value is the initial value. + */ + tmp = tcg_temp_new(); + tcg_gen_sub_i32(tmp, cpu_aregs[reg0], incr); + gen_store(s, opsize, addr, tmp); + tcg_temp_free(tmp); + } else { + gen_store(s, opsize, addr, mreg(i)); + } + } + } + tcg_gen_mov_i32(cpu_aregs[reg0], addr); + } else { + for (i = 0; i < 16; i++) { + if (mask & (1 << i)) { + gen_store(s, opsize, addr, mreg(i)); + tcg_gen_add_i32(addr, addr, incr); + } } - if (mask != 1) - tcg_gen_addi_i32(addr, addr, 4); } } + + tcg_temp_free(incr); + tcg_temp_free(addr); } DISAS_INSN(bitop_im) @@ -3822,7 +3904,9 @@ void register_m68k_insns (CPUM68KState *env) BASE(pea, 4840, ffc0); BASE(swap, 4840, fff8); INSN(bkpt, 4848, fff8, BKPT); - BASE(movem, 48c0, fbc0); + INSN(movem, 48d0, fbf8, CF_ISA_A); + INSN(movem, 48e8, fbf8, CF_ISA_A); + INSN(movem, 4880, fb80, M68000); BASE(ext, 4880, fff8); BASE(ext, 48c0, fff8); BASE(ext, 49c0, fff8);