From patchwork Sat Dec 24 11:40:29 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Laurent Vivier X-Patchwork-Id: 708657 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3tm3ZT0wHHz9t0G for ; Sat, 24 Dec 2016 22:54:08 +1100 (AEDT) Received: from localhost ([::1]:43178 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cKkto-0001kc-97 for incoming@patchwork.ozlabs.org; Sat, 24 Dec 2016 06:54:04 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:45447) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cKkh9-0007TQ-Kb for qemu-devel@nongnu.org; Sat, 24 Dec 2016 06:41:00 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1cKkh6-00084V-DD for qemu-devel@nongnu.org; Sat, 24 Dec 2016 06:40:59 -0500 Received: from mout.kundenserver.de ([217.72.192.74]:52487) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1cKkh6-00083o-1f for qemu-devel@nongnu.org; Sat, 24 Dec 2016 06:40:56 -0500 Received: from Quad.localdomain ([78.238.229.36]) by mrelayeu.kundenserver.de (mreue102 [212.227.15.183]) with ESMTPSA (Nemesis) id 0LlWdD-1cshrh3B1r-00bHJT; Sat, 24 Dec 2016 12:40:43 +0100 From: Laurent Vivier To: qemu-devel@nongnu.org Date: Sat, 24 Dec 2016 12:40:29 +0100 Message-Id: <1482579633-3393-9-git-send-email-laurent@vivier.eu> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1482579633-3393-1-git-send-email-laurent@vivier.eu> References: <1482579633-3393-1-git-send-email-laurent@vivier.eu> X-Provags-ID: V03:K0:Y0uq3AIlaLCKzukFSGV0UsoLZ4MCK6G/g7LyP4i3MHK8d4Jn4NC 3wDT1AiNPFGZ1RXa8vcaq8liTiocelDUl26xv01kh0qjjCajBn1a291/toseEzMO61JhHVN 1u6zuxq6kXdWEEfTXudrw/2cEvM89HHC2BRUimMeN+rEvowSX/M1wJPBl+kra4FH/+1LHii B/Dns3eRONqkCSHbQ6OJA== X-UI-Out-Filterresults: notjunk:1; V01:K0:5tFXpieFrNo=:apCRGLTSJKA9qSO78+WK9o J870fOORx0gYVfC4n5PM/fu6W0MUT3rah36BfM5udSrOZRqGfpljosJcVL/K7G8weF/LDOHJt ejdhrnQNrK/3FgRw6tX9Vr4MV5DwiP8kiFuR2H5DmmKzvHEhrgXxM6D6f+36npRiGy6nZBdam kefHmfd5VoSpFMSxzy41vzA+VlhByRysI5LxXGaRx8FzmtwoLh2xLdyqn+EqAL1yUz8TigSav hyUZ0bkS33gk17cWmRvrViGTLXF+N/IP20pv9qhuxHT9jfZ03XfWQNCfFO0pPx80BveKMLHPG ccNiw6+kPuuJBBkz0DwUuosy3saEKoEXhYFbdEHJYg7bu1tzSFh3WDMsXkL0DsHyBHX7I+5R+ u3sy8R2j8NOsOPdL+oqtM5fIlzH9bvziqWwYk2AOJcTSZ9wL6EqUwXUM9ZegCpYOHuhZPQZPs kqdxdIn1scM/obGCcB4dbTGXzDE++GiC7T5md+bGyOC0jg6ZD8QNf8M/+mtfpNqqlaVU3/ajr SyDxtnWpKrI52x5y5Xd2+Ek4T/WyR50IpD9Uk9TNtvOuA1gbDO74x4UN4eJZunnMmLEXwmicb 8ct4z4VfP3Jsv/gLfErpP25c97xpBipTTNkXhYzF8yiip3IKTlQjuxfuHRnjjtOjxeCCrn/0Z OqORSCpVRM+ZyeNC1IqOuwjotNADMEAzKlZi4y4fnYIYB19386hB//tzAro7VSai/vrM= X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 217.72.192.74 Subject: [Qemu-devel] [PULL 08/12] target-m68k: Implement 680x0 movem X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Laurent Vivier , Richard Henderson Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" 680x0 movem can load/store words and long words and can use more addressing modes. Coldfire can only use long words with (Ax) and (d16,Ax) addressing modes. Signed-off-by: Laurent Vivier Signed-off-by: Richard Henderson Message-Id: <1478699171-10637-2-git-send-email-rth@twiddle.net> --- target/m68k/translate.c | 130 +++++++++++++++++++++++++++++++++++++++--------- 1 file changed, 107 insertions(+), 23 deletions(-) diff --git a/target/m68k/translate.c b/target/m68k/translate.c index 0124820..acc8182 100644 --- a/target/m68k/translate.c +++ b/target/m68k/translate.c @@ -1645,40 +1645,122 @@ static void gen_push(DisasContext *s, TCGv val) tcg_gen_mov_i32(QREG_SP, tmp); } +static TCGv mreg(int reg) +{ + if (reg < 8) { + /* Dx */ + return cpu_dregs[reg]; + } + /* Ax */ + return cpu_aregs[reg & 7]; +} + DISAS_INSN(movem) { - TCGv addr; + TCGv addr, incr, tmp, r[16]; + int is_load = (insn & 0x0400) != 0; + int opsize = (insn & 0x40) != 0 ? OS_LONG : OS_WORD; + uint16_t mask = read_im16(env, s); + int mode = extract32(insn, 3, 3); + int reg0 = REG(insn, 0); int i; - uint16_t mask; - TCGv reg; - TCGv tmp; - int is_load; - mask = read_im16(env, s); - tmp = gen_lea(env, s, insn, OS_LONG); - if (IS_NULL_QREG(tmp)) { + tmp = cpu_aregs[reg0]; + + switch (mode) { + case 0: /* data register direct */ + case 1: /* addr register direct */ + do_addr_fault: gen_addr_fault(s); return; + + case 2: /* indirect */ + break; + + case 3: /* indirect post-increment */ + if (!is_load) { + /* post-increment is not allowed */ + goto do_addr_fault; + } + break; + + case 4: /* indirect pre-decrement */ + if (is_load) { + /* pre-decrement is not allowed */ + goto do_addr_fault; + } + /* We want a bare copy of the address reg, without any pre-decrement + adjustment, as gen_lea would provide. */ + break; + + default: + tmp = gen_lea_mode(env, s, mode, reg0, opsize); + if (IS_NULL_QREG(tmp)) { + goto do_addr_fault; + } + break; } + addr = tcg_temp_new(); tcg_gen_mov_i32(addr, tmp); - is_load = ((insn & 0x0400) != 0); - for (i = 0; i < 16; i++, mask >>= 1) { - if (mask & 1) { - if (i < 8) - reg = DREG(i, 0); - else - reg = AREG(i, 0); - if (is_load) { - tmp = gen_load(s, OS_LONG, addr, 0); - tcg_gen_mov_i32(reg, tmp); - } else { - gen_store(s, OS_LONG, addr, reg); + incr = tcg_const_i32(opsize_bytes(opsize)); + + if (is_load) { + /* memory to register */ + for (i = 0; i < 16; i++) { + if (mask & (1 << i)) { + r[i] = gen_load(s, opsize, addr, 1); + tcg_gen_add_i32(addr, addr, incr); + } + } + for (i = 0; i < 16; i++) { + if (mask & (1 << i)) { + tcg_gen_mov_i32(mreg(i), r[i]); + tcg_temp_free(r[i]); + } + } + if (mode == 3) { + /* post-increment: movem (An)+,X */ + tcg_gen_mov_i32(cpu_aregs[reg0], addr); + } + } else { + /* register to memory */ + if (mode == 4) { + /* pre-decrement: movem X,-(An) */ + for (i = 15; i >= 0; i--) { + if ((mask << i) & 0x8000) { + tcg_gen_sub_i32(addr, addr, incr); + if (reg0 + 8 == i && + m68k_feature(s->env, M68K_FEATURE_EXT_FULL)) { + /* M68020+: if the addressing register is the + * register moved to memory, the value written + * is the initial value decremented by the size of + * the operation, regardless of how many actual + * stores have been performed until this point. + * M68000/M68010: the value is the initial value. + */ + tmp = tcg_temp_new(); + tcg_gen_sub_i32(tmp, cpu_aregs[reg0], incr); + gen_store(s, opsize, addr, tmp); + tcg_temp_free(tmp); + } else { + gen_store(s, opsize, addr, mreg(i)); + } + } + } + tcg_gen_mov_i32(cpu_aregs[reg0], addr); + } else { + for (i = 0; i < 16; i++) { + if (mask & (1 << i)) { + gen_store(s, opsize, addr, mreg(i)); + tcg_gen_add_i32(addr, addr, incr); + } } - if (mask != 1) - tcg_gen_addi_i32(addr, addr, 4); } } + + tcg_temp_free(incr); + tcg_temp_free(addr); } DISAS_INSN(bitop_im) @@ -3822,7 +3904,9 @@ void register_m68k_insns (CPUM68KState *env) BASE(pea, 4840, ffc0); BASE(swap, 4840, fff8); INSN(bkpt, 4848, fff8, BKPT); - BASE(movem, 48c0, fbc0); + INSN(movem, 48d0, fbf8, CF_ISA_A); + INSN(movem, 48e8, fbf8, CF_ISA_A); + INSN(movem, 4880, fb80, M68000); BASE(ext, 4880, fff8); BASE(ext, 48c0, fff8); BASE(ext, 49c0, fff8);