From patchwork Sat Dec 3 05:00:04 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jose Ricardo Ziviani X-Patchwork-Id: 702248 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3tVzWb2sBRz9s2Q for ; Sat, 3 Dec 2016 16:06:18 +1100 (AEDT) Received: from localhost ([::1]:37759 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cD2We-0006Uy-7G for incoming@patchwork.ozlabs.org; Sat, 03 Dec 2016 00:06:16 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60046) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cD2RL-0001rd-6X for qemu-devel@nongnu.org; Sat, 03 Dec 2016 00:00:48 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1cD2RH-0005VU-1G for qemu-devel@nongnu.org; Sat, 03 Dec 2016 00:00:47 -0500 Received: from mx0b-001b2d01.pphosted.com ([148.163.158.5]:37487 helo=mx0a-001b2d01.pphosted.com) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1cD2RG-0005VN-Rm for qemu-devel@nongnu.org; Sat, 03 Dec 2016 00:00:42 -0500 Received: from pps.filterd (m0098417.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.17/8.16.0.17) with SMTP id uB34wkY0009761 for ; Sat, 3 Dec 2016 00:00:42 -0500 Received: from e24smtp04.br.ibm.com (e24smtp04.br.ibm.com [32.104.18.25]) by mx0a-001b2d01.pphosted.com with ESMTP id 273qdq0ct6-1 (version=TLSv1.2 cipher=AES256-SHA bits=256 verify=NOT) for ; Sat, 03 Dec 2016 00:00:42 -0500 Received: from localhost by e24smtp04.br.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; Sat, 3 Dec 2016 03:00:37 -0200 Received: from d24relay01.br.ibm.com (d24relay01.br.ibm.com [9.8.31.16]) by d24dlp01.br.ibm.com (Postfix) with ESMTP id 726D1352006C; Sat, 3 Dec 2016 00:00:06 -0500 (EST) Received: from d24av03.br.ibm.com (d24av03.br.ibm.com [9.8.31.95]) by d24relay01.br.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id uB350aJN4985028; Sat, 3 Dec 2016 03:00:36 -0200 Received: from d24av03.br.ibm.com (localhost [127.0.0.1]) by d24av03.br.ibm.com (8.14.4/8.14.4/NCO v10.0 AVout) with ESMTP id uB350Zlm004322; Sat, 3 Dec 2016 03:00:36 -0200 Received: from pacoca.ibm.com ([9.85.141.38]) by d24av03.br.ibm.com (8.14.4/8.14.4/NCO v10.0 AVin) with ESMTP id uB350HXN004194; Sat, 3 Dec 2016 03:00:33 -0200 From: Jose Ricardo Ziviani To: qemu-ppc@nongnu.org Date: Sat, 3 Dec 2016 03:00:04 -0200 X-Mailer: git-send-email 2.7.4 In-Reply-To: <1480741206-32737-1-git-send-email-joserz@linux.vnet.ibm.com> References: <1480741206-32737-1-git-send-email-joserz@linux.vnet.ibm.com> X-TM-AS-MML: disable X-Content-Scanned: Fidelis XPS MAILER x-cbid: 16120305-0028-0000-0000-000001776AE5 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 16120305-0029-0000-0000-00001471EE5B Message-Id: <1480741206-32737-6-git-send-email-joserz@linux.vnet.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:, , definitions=2016-12-03_03:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 suspectscore=1 malwarescore=0 phishscore=0 adultscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1609300000 definitions=main-1612030086 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [generic] [fuzzy] X-Received-From: 148.163.158.5 Subject: [Qemu-devel] [PATCH 5/7] target-ppc: Implement bcdsr. instruction X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: bharata@linux.vnet.ibm.com, qemu-devel@nongnu.org, nikunj@linux.vnet.ibm.com, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" bcdsr.: Decimal shift and round. This instruction works like bcds. however, when performing right shift, 1 will be added to the result if the last digit was >= 5. Signed-off-by: Jose Ricardo Ziviani --- target-ppc/helper.h | 1 + target-ppc/int_helper.c | 45 +++++++++++++++++++++++++++++++++++++ target-ppc/translate/vmx-impl.inc.c | 1 + target-ppc/translate/vmx-ops.inc.c | 2 ++ 4 files changed, 49 insertions(+) diff --git a/target-ppc/helper.h b/target-ppc/helper.h index 386ea67..d9528eb 100644 --- a/target-ppc/helper.h +++ b/target-ppc/helper.h @@ -394,6 +394,7 @@ DEF_HELPER_4(bcdcpsgn, i32, avr, avr, avr, i32) DEF_HELPER_3(bcdsetsgn, i32, avr, avr, i32) DEF_HELPER_4(bcds, i32, avr, avr, avr, i32) DEF_HELPER_4(bcdus, i32, avr, avr, avr, i32) +DEF_HELPER_4(bcdsr, i32, avr, avr, avr, i32) DEF_HELPER_2(xsadddp, void, env, i32) DEF_HELPER_2(xssubdp, void, env, i32) diff --git a/target-ppc/int_helper.c b/target-ppc/int_helper.c index 4b5eea1..c9fcb1a 100644 --- a/target-ppc/int_helper.c +++ b/target-ppc/int_helper.c @@ -3124,6 +3124,51 @@ uint32_t helper_bcdus(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, uint32_t ps) return cr; } +uint32_t helper_bcdsr(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, uint32_t ps) +{ + int cr; + int i; + int unused = 0; + int invalid = 0; + bool ox_flag = false; + int sgnb = bcd_get_sgn(b); + ppc_avr_t ret = *b; + ret.u64[LO_IDX] &= ~0xf; + +#if defined(HOST_WORDS_BIGENDIAN) + ppc_avr_t bcd_one = { .u64 = { 0, 0x10 } }; + int upper = ARRAY_SIZE(a->s32) - 1; +#else + ppc_avr_t bcd_one = { .u64 = { 0x10, 0 } }; + int upper = 0; +#endif + + if (bcd_is_valid(b) == false) { + return CRF_SO; + } + + if (a->s32[upper] > 0) { + i = (a->s32[upper] > 31) ? 31 : a->s32[upper]; + ulshift(&ret.u64[LO_IDX], &ret.u64[HI_IDX], i * 4, &ox_flag); + } else { + i = (a->s32[upper] < -31) ? 31 : -a->s32[upper]; + urshift(&ret.u64[LO_IDX], &ret.u64[HI_IDX], i * 4); + + if (bcd_get_digit(&ret, 0, &invalid) >= 5) { + bcd_add_mag(&ret, &ret, &bcd_one, &invalid, &unused); + } + } + bcd_put_digit(&ret, bcd_preferred_sgn(sgnb, ps), 0); + + cr = bcd_cmp_zero(&ret); + if (unlikely(ox_flag)) { + cr |= CRF_SO; + } + *r = ret; + + return cr; +} + void helper_vsbox(ppc_avr_t *r, ppc_avr_t *a) { int i; diff --git a/target-ppc/translate/vmx-impl.inc.c b/target-ppc/translate/vmx-impl.inc.c index fc54881..451abb5 100644 --- a/target-ppc/translate/vmx-impl.inc.c +++ b/target-ppc/translate/vmx-impl.inc.c @@ -1018,6 +1018,7 @@ GEN_BCD2(bcdsetsgn) GEN_BCD(bcdcpsgn); GEN_BCD(bcds); GEN_BCD(bcdus); +GEN_BCD(bcdsr); static void gen_xpnd04_1(DisasContext *ctx) { diff --git a/target-ppc/translate/vmx-ops.inc.c b/target-ppc/translate/vmx-ops.inc.c index cdd3abe..fa9c996 100644 --- a/target-ppc/translate/vmx-ops.inc.c +++ b/target-ppc/translate/vmx-ops.inc.c @@ -132,6 +132,8 @@ GEN_HANDLER_E_2(vprtybd, 0x4, 0x1, 0x18, 9, 0, PPC_NONE, PPC2_ISA300), GEN_HANDLER_E_2(vprtybq, 0x4, 0x1, 0x18, 10, 0, PPC_NONE, PPC2_ISA300), GEN_VXFORM_DUAL(vsubcuw, xpnd04_1, 0, 22, PPC_ALTIVEC, PPC_NONE), +GEN_VXFORM_300(bcdsr, 0, 23), +GEN_VXFORM_300(bcdsr, 0, 31), GEN_VXFORM_DUAL(vaddubs, vmul10uq, 0, 8, PPC_ALTIVEC, PPC_NONE), GEN_VXFORM_DUAL(vadduhs, vmul10euq, 0, 9, PPC_ALTIVEC, PPC_NONE), GEN_VXFORM(vadduws, 0, 10),