From patchwork Mon Nov 28 22:25:24 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Laurent Vivier X-Patchwork-Id: 700176 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3tSLr90t4vz9vDw for ; Tue, 29 Nov 2016 09:26:32 +1100 (AEDT) Received: from localhost ([::1]:33432 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cBUNZ-000751-Kx for incoming@patchwork.ozlabs.org; Mon, 28 Nov 2016 17:26:29 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:47069) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cBUMv-0006lk-ON for qemu-devel@nongnu.org; Mon, 28 Nov 2016 17:25:50 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1cBUMs-0006Zs-Fv for qemu-devel@nongnu.org; Mon, 28 Nov 2016 17:25:49 -0500 Received: from mout.kundenserver.de ([212.227.126.135]:59167) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1cBUMs-0006WV-2Z for qemu-devel@nongnu.org; Mon, 28 Nov 2016 17:25:46 -0500 Received: from Quad.localdomain ([78.238.229.36]) by mrelayeu.kundenserver.de (mreue005 [212.227.15.167]) with ESMTPSA (Nemesis) id 0ME20p-1bvme52KOl-00HN20; Mon, 28 Nov 2016 23:25:38 +0100 From: Laurent Vivier To: qemu-devel@nongnu.org Date: Mon, 28 Nov 2016 23:25:24 +0100 Message-Id: <1480371924-468-1-git-send-email-laurent@vivier.eu> X-Mailer: git-send-email 2.7.4 X-Provags-ID: V03:K0:uYp33UBE638D/Lt+AFvFwLAmCyayHFre5E0pSyxp0U16bcrAGsI Vh8AmEvF0LUeuiPwp1QWxxh+aNLYuRq2Y6lGta+c84nB2nJbkx0Ujve8sn/GCp3Fkhrdkal grYPeAWn+4fKMXzGWPrfBr5rnZHHr8SZ1kyMI44qYDM5tsOq+AKK/YMdQpXQ1Gfcm+6SS4i RGMK37AW3UOwwv+j9jSKQ== X-UI-Out-Filterresults: notjunk:1; V01:K0:cl63OIQ8/qI=:91OMgQwN2sfw+M70Sc0W/x cy030D6S0buCWDSlHRhznXQfuoUdmhHffT+d6s+MKTeMq0Ca1JBKLCIvNgKVgq3yT7dNB7lTa opAEuqIbskgeUm1n7HAJaJSRjN85SRh2E64gKFVOStoOHnIwjFpx08RH/ZFtD3eDpEBDIkOHX +ayWpkuor2Apy1C2R+VEoS9LAGvjD6m//ebNPnejtleqrfMr8iKtqfPJJ1BAzpiKK/t3HVugS xMUrdc0pb3gzYF+XRSSqDFK4Ijw09zdrlfT60TZYR/CoygWVE7x0PupFfXjI3rJyFH5kJN4EN /lSHh5pq0QqgbQNUJURfktANzy956HYdalhLTuutWqJDJxWwRai8ZD9s0LZKjjryNA8z40Mly B6+1F72Iy7XKPF+4pF+BCyKhg5oV8a1zh2Ty3EJCOzPt7QnIIpbHsspiNuC0tr4+joUJsYHiV FUWbUkzZQoukmE5h0+mN7FFP/O0tytyEDexNwxZZ/XTNIAcy1V+1Um5ta6+ueTpNSnLo1dvlc xNoLI1Qs6ecf/kCy/9Xdok6T0nvxDcqx6LInNGMqeTK0Pf52A17F7p6HjwE9GA+4mmWNtAnRF S6x4kG8DvSjeEgzct+kHSOFfoWTxjvLrgssG5+vnZc4j5bBpqmyALToDAN9N74bzzqk2Gckle hTbOf63/2GUB0nGQa8+IYSh1QT+/s9rPPegADJ0ausy7tFc8VZYzObJCWKiAt3PcCHPc= X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 212.227.126.135 Subject: [Qemu-devel] [PATCH] target-m68k: fix CAS X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Laurent Vivier , Richard Henderson Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" - update flags before setting the result to cmp, because after that cmp == load and flags are always Z, - comparison is signed, so use signed values, - move "cas" after arith_im in the table, otherwise casw can be decoded as an arith_im. Signed-off-by: Laurent Vivier --- NOTE: this patch applies to my branch m68k-for-2.9, once reviewed I will merge it with the patch already in the branch, "target-m68k: add cas/cas2 ops" I've checked CAS2, but I didn't find any problem. target-m68k/translate.c | 21 +++++++++++---------- 1 file changed, 11 insertions(+), 10 deletions(-) diff --git a/target-m68k/translate.c b/target-m68k/translate.c index ffa987d..c7c881c 100644 --- a/target-m68k/translate.c +++ b/target-m68k/translate.c @@ -2216,15 +2216,15 @@ DISAS_INSN(cas) switch ((insn >> 9) & 3) { case 1: opsize = OS_BYTE; - opc = MO_UB; + opc = MO_SB; break; case 2: opsize = OS_WORD; - opc = MO_TEUW; + opc = MO_TESW; break; case 3: opsize = OS_LONG; - opc = MO_TEUL; + opc = MO_TESL; break; default: g_assert_not_reached(); @@ -2241,7 +2241,7 @@ DISAS_INSN(cas) return; } - cmp = gen_extend(DREG(ext, 0), opsize, 0); + cmp = gen_extend(DREG(ext, 0), opsize, 1); /* if == Dc then * = Du @@ -2253,9 +2253,10 @@ DISAS_INSN(cas) load = tcg_temp_new(); tcg_gen_atomic_cmpxchg_i32(load, addr, cmp, DREG(ext, 6), IS_USER(s), opc); + /* update flags before setting cmp to load */ + gen_update_cc_cmp(s, load, cmp, opsize); gen_partset_reg(opsize, DREG(ext, 0), load); - gen_update_cc_cmp(s, load, cmp, opsize); tcg_temp_free(load); } @@ -5337,17 +5338,17 @@ void register_m68k_insns (CPUM68KState *env) INSN(arith_im, 0680, fff8, CF_ISA_A); INSN(arith_im, 0c00, ff38, CF_ISA_A); INSN(arith_im, 0c00, ff00, M68000); - INSN(cas, 0ac0, ffc0, CAS); - INSN(cas, 0cc0, ffc0, CAS); - INSN(cas, 0ec0, ffc0, CAS); - INSN(cas2w, 0cfc, ffff, CAS); - INSN(cas2l, 0efc, ffff, CAS); BASE(bitop_im, 0800, ffc0); BASE(bitop_im, 0840, ffc0); BASE(bitop_im, 0880, ffc0); BASE(bitop_im, 08c0, ffc0); INSN(arith_im, 0a80, fff8, CF_ISA_A); INSN(arith_im, 0a00, ff00, M68000); + INSN(cas, 0ac0, ffc0, CAS); + INSN(cas, 0cc0, ffc0, CAS); + INSN(cas, 0ec0, ffc0, CAS); + INSN(cas2w, 0cfc, ffff, CAS); + INSN(cas2l, 0efc, ffff, CAS); BASE(move, 1000, f000); BASE(move, 2000, f000); BASE(move, 3000, f000);