From patchwork Thu Nov 10 22:51:24 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Laurent Vivier X-Patchwork-Id: 693494 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3tFJJn0Syzz9t10 for ; Fri, 11 Nov 2016 09:54:33 +1100 (AEDT) Received: from localhost ([::1]:49750 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1c4yEm-0006Mj-6h for incoming@patchwork.ozlabs.org; Thu, 10 Nov 2016 17:54:28 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:45596) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1c4yC6-0004UH-Qp for qemu-devel@nongnu.org; Thu, 10 Nov 2016 17:51:44 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1c4yC2-0006Kj-T0 for qemu-devel@nongnu.org; Thu, 10 Nov 2016 17:51:42 -0500 Received: from mout.kundenserver.de ([212.227.17.24]:53018) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1c4yC2-0006Ji-Ix for qemu-devel@nongnu.org; Thu, 10 Nov 2016 17:51:38 -0500 Received: from Quad.localdomain ([78.238.229.36]) by mrelayeu.kundenserver.de (mreue104 [212.227.15.183]) with ESMTPSA (Nemesis) id 0MJCxO-1c7iHY2En4-002ph8; Thu, 10 Nov 2016 23:51:30 +0100 From: Laurent Vivier To: qemu-devel@nongnu.org Date: Thu, 10 Nov 2016 23:51:24 +0100 Message-Id: <1478818284-9482-1-git-send-email-laurent@vivier.eu> X-Mailer: git-send-email 2.7.4 X-Provags-ID: V03:K0:/YsLPPxivNHRC07lx+HyIvx6BPO1r+be8YxG74mRmpCstYwUefn u429ZaaNN9vM03gQJ4zGaxUMzo81CeleEUHFkyOIW5BwzMlozJMlxB+geghyYdkqy4eq9zy 2IqGsgIPTHlTYOBFkdc3VGUdQmvnB5AZ8zL8oYBYxaM+YjutAl2hxmR7KdMdy0SekZORnY2 EyqyjAvAR057w7PXOSmlQ== X-UI-Out-Filterresults: notjunk:1; V01:K0:37XDd/YyRHM=:ZDe/HwNF7a2jIvQ+NNQd3G MFC9HYl5c33TKq9gYKVYtdW/cHASo7L2ThWRyZwP+KN2Q3gH/3R/mw3qMW0TCHwvN0hAqsIYr JX8f2A9o20jZRg6RWwe4UgScFAPDF/Dv9fLIPNS3nCpgWpEdLQknqE57+j5Cw7uhJf+iXx+N5 cJEiP+aoLlZhvY+ctypDZXLsbN3LrXWE0IzGCv6pL+bLjieKxk0cInELtgZGOsqnkaqcu2f7D SZQXf/z+juTyflis1iOZ1vPJAaaJyjGBl5lW68t/IjZhlGqrbtO4+75J2oW2ah1SKLU8Syyr3 +/hKoSQpM0HpeLYY4mj96FLgOUMNqeF2GsZjVcjN4x8Kt9yisjZZMu1CRcsktKxwRF1xXKPXf eOqI97gtyIeiPutEj6aNsvu3zWyOQcYj0FoZEdxviSfr3eUyuPj07XSTbghISgjGsSE5iVVgn b7Oy6LRq9N3XwjeaDjnhIa9LKSGsAVQkMwkc2b7B5aWTX4Up662RFH9dRkWt217N0HOSvUbVq JQ51jiwkVePE7QaFfo0tEYYF1E+KcSEjVXv4bDvcoVrwk56WX6AOE22b0BOW26TVSfv5Z3kn8 fh/hL+4Adhb6/i9nbsUmx18m1I2RrB4WsbXUnjmVhUok90XpqdqW2/iAqV47c9MjKtmKL3XZ+ 2qkwHfCotKnvFEhLtY37fRC0nEqBfN9CVrIlsF+LgifZ/vwNmOprFe5QrRMmSGluSems= X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 212.227.17.24 Subject: [Qemu-devel] [PATCH v2] target-m68k: add rol/ror/roxl/roxr instructions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Laurent Vivier , Richard Henderson Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Laurent Vivier --- v2: - use shift to do rotate_x() for 8 and 16bit value - rotate_x()/rotate32_x() are a no-op when shift % (size + 1) == 0 - add some missing tcg_temp_free() target-m68k/translate.c | 414 ++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 414 insertions(+) diff --git a/target-m68k/translate.c b/target-m68k/translate.c index 96af672..0a85dc4 100644 --- a/target-m68k/translate.c +++ b/target-m68k/translate.c @@ -3080,6 +3080,413 @@ DISAS_INSN(shift_mem) set_cc_op(s, CC_OP_FLAGS); } +static void rotate(TCGv reg, TCGv shift, int left, int size) +{ + switch (size) { + case 8: + /* Replicate the 8-bit input so that a 32-bit rotate works. */ + tcg_gen_ext8u_i32(reg, reg); + tcg_gen_muli_i32(reg, reg, 0x01010101); + goto do_long; + case 16: + /* Replicate the 16-bit input so that a 32-bit rotate works. */ + tcg_gen_deposit_i32(reg, reg, reg, 16, 16); + goto do_long; + do_long: + default: + if (left) { + tcg_gen_rotl_i32(reg, reg, shift); + } else { + tcg_gen_rotr_i32(reg, reg, shift); + } + } + + /* compute flags */ + + switch (size) { + case 8: + tcg_gen_ext8s_i32(reg, reg); + break; + case 16: + tcg_gen_ext16s_i32(reg, reg); + break; + default: + break; + } + + /* QREG_CC_X is not affected */ + + tcg_gen_mov_i32(QREG_CC_N, reg); + tcg_gen_mov_i32(QREG_CC_Z, reg); + + if (left) { + tcg_gen_andi_i32(QREG_CC_C, reg, 1); + } else { + tcg_gen_shri_i32(QREG_CC_C, reg, 31); + } + + tcg_gen_movi_i32(QREG_CC_V, 0); /* always cleared */ +} + +static void rotate_x_flags(TCGv reg, TCGv X, int size) +{ + switch (size) { + case 8: + tcg_gen_ext8s_i32(reg, reg); + break; + case 16: + tcg_gen_ext16s_i32(reg, reg); + break; + default: + break; + } + tcg_gen_mov_i32(QREG_CC_N, reg); + tcg_gen_mov_i32(QREG_CC_Z, reg); + tcg_gen_mov_i32(QREG_CC_X, X); + tcg_gen_mov_i32(QREG_CC_C, X); + tcg_gen_movi_i32(QREG_CC_V, 0); +} + +/* Result of rotate_x() is valid if 0 < shift < (size + 1) < 32 */ +static TCGv rotate_x(TCGv dest, TCGv src, TCGv shift, int left, int size) +{ + TCGv X, shl, shr, shx; + + shr = tcg_temp_new(); + shl = tcg_temp_new(); + shx = tcg_temp_new(); + if (left) { + tcg_gen_mov_i32(shl, shift); /* shl = shift */ + tcg_gen_movi_i32(shr, size + 1); + tcg_gen_sub_i32(shr, shr, shift); /* shr = size + 1 - shift */ + tcg_gen_subi_i32(shx, shift, 1); /* shx = shift - 1 */ + } else { + tcg_gen_mov_i32(shr, shift); /* shr = shift */ + tcg_gen_movi_i32(shl, size + 1); + tcg_gen_sub_i32(shl, shl, shift); /* shl = size + 1 - shift */ + tcg_gen_movi_i32(shx, size); + tcg_gen_sub_i32(shx, shx, shift); /* shx = size - shift */ + } + + /* dest = (src << shl) | (src >> shr) | (x << shx); */ + + tcg_gen_shl_i32(shl, src, shl); + tcg_gen_shr_i32(shr, src, shr); + tcg_gen_or_i32(dest, shl, shr); + tcg_temp_free(shl); + tcg_temp_free(shr); + tcg_gen_shl_i32(shx, QREG_CC_X, shx); + tcg_gen_or_i32(dest, dest, shx); + tcg_temp_free(shx); + + /* X = (dest >> size) & 1 */ + + X = tcg_temp_new(); + tcg_gen_shri_i32(X, dest, size); + tcg_gen_andi_i32(X, X, 1); + + return X; +} + +/* Result of rotate32_x() is valid if 0 < shift < 33 */ +static TCGv rotate32_x(TCGv dest, TCGv src, TCGv shift, int left) +{ + TCGv_i64 t0, shift64; + TCGv X, lo, hi; + + shift64 = tcg_temp_new_i64(); + tcg_gen_extu_i32_i64(shift64, shift); + + t0 = tcg_temp_new_i64(); + + X = tcg_temp_new(); + lo = tcg_temp_new(); + hi = tcg_temp_new(); + + if (left) { + /* create [src:X:..] */ + + tcg_gen_shli_i32(lo, QREG_CC_X, 31); + tcg_gen_concat_i32_i64(t0, lo, src); + + /* rotate */ + + tcg_gen_rotl_i64(t0, t0, shift64); + tcg_temp_free_i64(shift64); + + /* result is [src:..:src:X] */ + + tcg_gen_extr_i64_i32(lo, hi, t0); + tcg_gen_andi_i32(X, lo, 1); + + tcg_gen_shri_i32(lo, lo, 1); + } else { + /* create [..:X:src] */ + + tcg_gen_concat_i32_i64(t0, src, QREG_CC_X); + + tcg_gen_rotr_i64(t0, t0, shift64); + tcg_temp_free_i64(shift64); + + /* result is value: [X:src:..:src] */ + + tcg_gen_extr_i64_i32(lo, hi, t0); + + /* extract X */ + + tcg_gen_shri_i32(X, hi, 31); + + /* extract result */ + + tcg_gen_shli_i32(hi, hi, 1); + } + tcg_gen_or_i32(dest, lo, hi); + tcg_temp_free(hi); + tcg_temp_free(lo); + tcg_temp_free_i64(t0); + + return X; +} + +DISAS_INSN(rotate_im) +{ + TCGv shift; + int tmp; + int left = (insn & 0x100); + + tmp = (insn >> 9) & 7; + if (tmp == 0) { + tmp = 8; + } + + shift = tcg_const_i32(tmp); + if (insn & 8) { + rotate(DREG(insn, 0), shift, left, 32); + } else { + TCGv X = rotate32_x(DREG(insn, 0), DREG(insn, 0), shift, left); + rotate_x_flags(DREG(insn, 0), X, 32); + tcg_temp_free(X); + } + tcg_temp_free(shift); + + set_cc_op(s, CC_OP_FLAGS); +} + +DISAS_INSN(rotate8_im) +{ + int left = (insn & 0x100); + TCGv reg; + TCGv shift; + int tmp; + + reg = gen_extend(DREG(insn, 0), OS_BYTE, 0); + + tmp = (insn >> 9) & 7; + if (tmp == 0) { + tmp = 8; + } + + shift = tcg_const_i32(tmp); + if (insn & 8) { + rotate(reg, shift, left, 8); + } else { + TCGv X = rotate_x(reg, reg, shift, left, 8); + rotate_x_flags(reg, X, 8); + tcg_temp_free(X); + } + tcg_temp_free(shift); + gen_partset_reg(OS_BYTE, DREG(insn, 0), reg); + set_cc_op(s, CC_OP_FLAGS); +} + +DISAS_INSN(rotate16_im) +{ + int left = (insn & 0x100); + TCGv reg; + TCGv shift; + int tmp; + + reg = gen_extend(DREG(insn, 0), OS_WORD, 0); + tmp = (insn >> 9) & 7; + if (tmp == 0) { + tmp = 8; + } + + shift = tcg_const_i32(tmp); + if (insn & 8) { + rotate(reg, shift, left, 16); + } else { + TCGv X = rotate_x(reg, reg, shift, left, 16); + rotate_x_flags(reg, X, 8); + tcg_temp_free(X); + } + tcg_temp_free(shift); + gen_partset_reg(OS_WORD, DREG(insn, 0), reg); + set_cc_op(s, CC_OP_FLAGS); +} + +DISAS_INSN(rotate_reg) +{ + TCGv reg; + TCGv src; + TCGv t0, t1; + int left = (insn & 0x100); + + reg = DREG(insn, 0); + src = DREG(insn, 9); + t0 = tcg_temp_new(); + t1 = tcg_temp_new_i32(); + if (insn & 8) { + tcg_gen_andi_i32(t0, src, 63); + tcg_gen_andi_i32(t1, src, 31); + rotate(reg, t1, left, 32); + /* if shift == 0, clear C */ + tcg_gen_movcond_i32(TCG_COND_EQ, QREG_CC_C, + t0, QREG_CC_V /* 0 */, + QREG_CC_V /* 0 */, QREG_CC_C); + } else { + TCGv X, zero, res; + /* shift in [0..63] */ + tcg_gen_andi_i32(t0, src, 63); + /* modulo 33 */ + tcg_gen_movi_i32(t1, 33); + tcg_gen_remu_i32(t1, t0, t1); + res = tcg_temp_new(); + X = rotate32_x(res, DREG(insn, 0), t1, left); + /* if shift % 33 == 0, register and X are not affected */ + zero = tcg_const_i32(0); + tcg_gen_movcond_i32(TCG_COND_EQ, X, + t1, zero, + QREG_CC_X, X); + tcg_gen_movcond_i32(TCG_COND_EQ, DREG(insn, 0), + t1, zero, + DREG(insn, 0), res); + tcg_temp_free(res); + tcg_temp_free(zero); + rotate_x_flags(DREG(insn, 0), X, 32); + tcg_temp_free(X); + } + tcg_temp_free(t1); + tcg_temp_free(t0); + set_cc_op(s, CC_OP_FLAGS); +} + +DISAS_INSN(rotate8_reg) +{ + TCGv reg; + TCGv src; + TCGv t0, t1; + int left = (insn & 0x100); + + reg = gen_extend(DREG(insn, 0), OS_BYTE, 0); + src = DREG(insn, 9); + t0 = tcg_temp_new_i32(); + t1 = tcg_temp_new_i32(); + if (insn & 8) { + tcg_gen_andi_i32(t0, src, 63); + tcg_gen_andi_i32(t1, src, 7); + rotate(reg, t1, left, 8); + /* if shift == 0, clear C */ + tcg_gen_movcond_i32(TCG_COND_EQ, QREG_CC_C, + t0, QREG_CC_V /* 0 */, + QREG_CC_V /* 0 */, QREG_CC_C); + } else { + TCGv X, res, zero; + /* shift in [0..63] */ + tcg_gen_andi_i32(t0, src, 63); + /* modulo 9 */ + tcg_gen_movi_i32(t1, 9); + tcg_gen_remu_i32(t1, t0, t1); + res = tcg_temp_new(); + X = rotate_x(res, reg, t1, left, 8); + /* if shift % 9 == 0, register and X are not affected */ + zero = tcg_const_i32(0); + tcg_gen_movcond_i32(TCG_COND_EQ, X, + t1, zero, + QREG_CC_X, X); + tcg_gen_movcond_i32(TCG_COND_EQ, reg, + t1, zero, + reg, res); + tcg_temp_free(res); + tcg_temp_free(zero); + rotate_x_flags(reg, X, 8); + tcg_temp_free(X); + } + tcg_temp_free(t1); + tcg_temp_free(t0); + gen_partset_reg(OS_BYTE, DREG(insn, 0), reg); + set_cc_op(s, CC_OP_FLAGS); +} + +DISAS_INSN(rotate16_reg) +{ + TCGv reg; + TCGv src; + TCGv t0, t1; + int left = (insn & 0x100); + + reg = gen_extend(DREG(insn, 0), OS_WORD, 0); + src = DREG(insn, 9); + t0 = tcg_temp_new_i32(); + t1 = tcg_temp_new_i32(); + if (insn & 8) { + tcg_gen_andi_i32(t0, src, 63); + tcg_gen_andi_i32(t1, src, 15); + rotate(reg, t1, left, 16); + /* if shift == 0, clear C */ + tcg_gen_movcond_i32(TCG_COND_EQ, QREG_CC_C, + t0, QREG_CC_V /* 0 */, + QREG_CC_V /* 0 */, QREG_CC_C); + } else { + TCGv X, res, zero; + /* shift in [0..63] */ + tcg_gen_andi_i32(t0, src, 63); + /* modulo 17 */ + t1 = tcg_const_i32(17); + tcg_gen_remu_i32(t1, t0, t1); + res = tcg_temp_new(); + X = rotate_x(res, reg, t1, left, 16); + /* if shift % 17 == 0, register and X are not affected */ + zero = tcg_const_i32(0); + tcg_gen_movcond_i32(TCG_COND_EQ, X, + t1, zero, + QREG_CC_X, X); + tcg_gen_movcond_i32(TCG_COND_EQ, reg, + t1, zero, + reg, res); + tcg_temp_free(res); + tcg_temp_free(zero); + rotate_x_flags(reg, X, 16); + tcg_temp_free(X); + } + tcg_temp_free(t1); + tcg_temp_free(t0); + gen_partset_reg(OS_WORD, DREG(insn, 0), reg); + set_cc_op(s, CC_OP_FLAGS); +} + +DISAS_INSN(rotate_mem) +{ + TCGv src; + TCGv addr; + TCGv shift; + int left = (insn & 0x100); + + SRC_EA(env, src, OS_WORD, 0, &addr); + + shift = tcg_const_i32(1); + if (insn & 8) { + rotate(src, shift, left, 16); + } else { + TCGv X = rotate_x(src, src, shift, left, 16); + rotate_x_flags(src, X, 16); + tcg_temp_free(X); + } + tcg_temp_free(shift); + DEST_EA(env, insn, OS_WORD, src, &addr); + set_cc_op(s, CC_OP_FLAGS); +} + static void bitfield_param(uint16_t ext, TCGv *offset, TCGv *width, TCGv *mask) { TCGv tmp; @@ -4492,6 +4899,13 @@ void register_m68k_insns (CPUM68KState *env) INSN(shift16_reg, e060, f0f0, M68000); INSN(shift_reg, e0a0, f0f0, M68000); INSN(shift_mem, e0c0, fcc0, M68000); + INSN(rotate_im, e090, f0f0, M68000); + INSN(rotate8_im, e010, f0f0, M68000); + INSN(rotate16_im, e050, f0f0, M68000); + INSN(rotate_reg, e0b0, f0f0, M68000); + INSN(rotate8_reg, e030, f0f0, M68000); + INSN(rotate16_reg, e070, f0f0, M68000); + INSN(rotate_mem, e4c0, fcc0, M68000); INSN(bitfield_mem,e8c0, f8c0, BITFIELD); INSN(bitfield_reg,e8c0, f8f8, BITFIELD); INSN(undef_fpu, f000, f000, CF_ISA_A);