From patchwork Tue Nov 8 13:25:27 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Laurent Vivier X-Patchwork-Id: 692298 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3tCqtk5xzWz9t0w for ; Wed, 9 Nov 2016 00:30:22 +1100 (AEDT) Received: from localhost ([::1]:32996 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1c46Tk-0005Uq-F0 for incoming@patchwork.ozlabs.org; Tue, 08 Nov 2016 08:30:20 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36895) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1c46PN-0001pE-Mg for qemu-devel@nongnu.org; Tue, 08 Nov 2016 08:25:53 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1c46PJ-0007fF-ML for qemu-devel@nongnu.org; Tue, 08 Nov 2016 08:25:49 -0500 Received: from mout.kundenserver.de ([212.227.126.130]:56881) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1c46PJ-0007ee-BO for qemu-devel@nongnu.org; Tue, 08 Nov 2016 08:25:45 -0500 Received: from Quad.localdomain ([78.238.229.36]) by mrelayeu.kundenserver.de (mreue003) with ESMTPSA (Nemesis) id 0Lxrpw-1crPmU1NuG-015GOf; Tue, 08 Nov 2016 14:25:34 +0100 From: Laurent Vivier To: qemu-devel@nongnu.org Date: Tue, 8 Nov 2016 14:25:27 +0100 Message-Id: <1478611528-24643-2-git-send-email-laurent@vivier.eu> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1478611528-24643-1-git-send-email-laurent@vivier.eu> References: <1478611528-24643-1-git-send-email-laurent@vivier.eu> X-Provags-ID: V03:K0:zneKYQjW5T1vpN/iasJAi7WO32TAMk2RebfT31OgjQB+/jotuVA uvitdYbkimFHfZdQetQOnb6ZlCU41A3DXZFSeUOBufl8UWiecwhRBfRhJvzheRxToglbzH5 ALxntwre7tQEXded48eKWTo/FozWCsm+QDVVDin7WfutAvthDrqrB8GxOb344Ncf6h+qWDY 677WDzigr89yD+ZSyJMhg== X-UI-Out-Filterresults: notjunk:1; V01:K0:EkJTu9ncCvU=:IkDO8ou0zTnfahu4UCwfmz ja4PbSDJ1JHEu4ZAgd4iX75uOzp6NKE9Du/hJrdCndvXBO3wPHuarSpZePQQ6az3kbPLx4PHs u9LQhClEc5A1IvTWtMvel4Y/Erh4l2ShR5i2N+3XEO+mUgF74ia0/+LgeCE8rI6sGFDlqJFCH /cMXt+Ix5E4yO9W2q/twIJYmVQqZfD5cIRXeFwkXPmSGyL4eD2OevaYkhCpIs+UxHvVI9ZjAv M/ZERuV93fiirvCXG+9QD5NvbVu2uZzBF5B+eRNw7u/fjTciFqZoeecXmeVfiUZFYFlAWjoC5 hZT6BS6EoRrDUwY5QRYslcTfpzYK2kQFSwBQx5WBD2dZu+c4QWOsOJusibuINBsDf2T0UJvFp PUVisa/VXy/su7Nzq7VJwhqr+yO43bgCziF2dIHVczaMnWetl52yY4BkC3z0frIVSeOBCH4Pb 7uBnWyLPSnl51F6XXqdIFSJgCw+AcIPgiyVWevWdnSLifCKiTRnXY6+heiSG86LJA4kVWzkXD lidArB3F29rQJSWVnHm/nEleFIVkmAkfTx8sIgI1KAdwJOnu2pGPdeBQbjy7Hc7rb+qVTK9Nt vP/ITs7rcElAeYqehZ6s0liiC5NKucQ4BYb9814Cu8sNE+jtfJGL8mv6lg4etwFpzyhyj1Now Px1YrtQFJcRQFJ8jaG5cGPfT1ofMhq+Td/K/mj8yABmg+pN2KNSj/QbHKNDuVDA+Yzj4= X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 212.227.126.130 Subject: [Qemu-devel] [PATCH v4 1/2] target-m68k: add abcd/sbcd/nbcd X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Laurent Vivier , gerg@uclinux.org, schwab@linux-m68k.org, agraf@suse.de, Richard Henderson Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Laurent Vivier Reviewed-by: Richard Henderson Reviewed-by: Richard Henderson --- target-m68k/translate.c | 216 ++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 216 insertions(+) diff --git a/target-m68k/translate.c b/target-m68k/translate.c index b538d74..f4eba90 100644 --- a/target-m68k/translate.c +++ b/target-m68k/translate.c @@ -1315,6 +1315,217 @@ DISAS_INSN(divl) set_cc_op(s, CC_OP_FLAGS); } +static void bcd_add(TCGv dest, TCGv src) +{ + TCGv t0, t1; + + /* dest10 = dest10 + src10 + X + * + * t1 = src + * t2 = t1 + 0x066 + * t3 = t2 + dest + X + * t4 = t2 ^ dest + * t5 = t3 ^ t4 + * t6 = ~t5 & 0x110 + * t7 = (t6 >> 2) | (t6 >> 3) + * return t3 - t7 + */ + + /* t1 = (src + 0x066) + dest + X + * = result with some possible exceding 0x6 + */ + + t0 = tcg_const_i32(0x066); + tcg_gen_add_i32(t0, t0, src); + + t1 = tcg_temp_new(); + tcg_gen_add_i32(t1, t0, dest); + tcg_gen_add_i32(t1, t1, QREG_CC_X); + + /* we will remove exceding 0x6 where there is no carry */ + + /* t0 = (src + 0x0066) ^ dest + * = t1 without carries + */ + + tcg_gen_xor_i32(t0, t0, dest); + + /* extract the carries + * t0 = t0 ^ t1 + * = only the carries + */ + + tcg_gen_xor_i32(t0, t0, t1); + + /* generate 0x1 where there is no carry + * and for each 0x10, generate a 0x6 + */ + + tcg_gen_shri_i32(t0, t0, 3); + tcg_gen_not_i32(t0, t0); + tcg_gen_andi_i32(t0, t0, 0x22); + tcg_gen_add_i32(dest, t0, t0); + tcg_gen_add_i32(dest, dest, t0); + + /* remove the exceding 0x6 + * for digits that have not generated a carry + */ + + tcg_gen_sub_i32(dest, t1, dest); + tcg_temp_free(t1); +} + +static void bcd_sub(TCGv dest, TCGv src) +{ + TCGv t0, t1, t2; + + /* dest10 = dest10 - src10 - X + * = bcd_add(dest + 1 - X, 0x199 - src) + */ + + /* t0 = 0x066 + (0x199 - src) */ + + t0 = tcg_temp_new(); + tcg_gen_subfi_i32(t0, 0x1ff, src); + + /* t1 = t0 + dest + 1 - X*/ + + t1 = tcg_temp_new(); + tcg_gen_add_i32(t1, t0, dest); + tcg_gen_addi_i32(t1, t1, 1); + tcg_gen_sub_i32(t1, t1, QREG_CC_X); + + /* t2 = t0 ^ dest */ + + t2 = tcg_temp_new(); + tcg_gen_xor_i32(t2, t0, dest); + + /* t0 = t1 ^ t2 */ + + tcg_gen_xor_i32(t0, t1, t2); + + /* t2 = ~t0 & 0x110 + * t0 = (t2 >> 2) | (t2 >> 3) + * + * to fit on 8bit operands, changed in: + * + * t2 = ~(t0 >> 3) & 0x22 + * t0 = t2 + t2 + * t0 = t0 + t2 + */ + + tcg_gen_shri_i32(t2, t0, 3); + tcg_gen_not_i32(t2, t2); + tcg_gen_andi_i32(t2, t2, 0x22); + tcg_gen_add_i32(t0, t2, t2); + tcg_gen_add_i32(t0, t0, t2); + + /* return t1 - t0 */ + + tcg_gen_sub_i32(dest, t1, t0); +} + +static void bcd_flags(TCGv val) +{ + tcg_gen_andi_i32(QREG_CC_C, val, 0x0ff); + tcg_gen_or_i32(QREG_CC_Z, QREG_CC_Z, QREG_CC_C); + + tcg_gen_shri_i32(QREG_CC_C, val, 8); + tcg_gen_andi_i32(QREG_CC_C, QREG_CC_C, 1); + + tcg_gen_mov_i32(QREG_CC_X, QREG_CC_C); +} + +DISAS_INSN(abcd_reg) +{ + TCGv src; + TCGv dest; + + gen_flush_flags(s); /* !Z is sticky */ + + src = gen_extend(DREG(insn, 0), OS_BYTE, 0); + dest = gen_extend(DREG(insn, 9), OS_BYTE, 0); + bcd_add(dest, src); + gen_partset_reg(OS_BYTE, DREG(insn, 9), dest); + + bcd_flags(dest); +} + +DISAS_INSN(abcd_mem) +{ + TCGv src, dest, addr; + + gen_flush_flags(s); /* !Z is sticky */ + + /* Indirect pre-decrement load (mode 4) */ + + src = gen_ea_mode(env, s, 4, REG(insn, 0), OS_BYTE, + NULL_QREG, NULL, EA_LOADU); + dest = gen_ea_mode(env, s, 4, REG(insn, 9), OS_BYTE, + NULL_QREG, &addr, EA_LOADU); + + bcd_add(dest, src); + + gen_ea_mode(env, s, 4, REG(insn, 9), OS_BYTE, dest, &addr, EA_STORE); + + bcd_flags(dest); +} + +DISAS_INSN(sbcd_reg) +{ + TCGv src, dest; + + gen_flush_flags(s); /* !Z is sticky */ + + src = gen_extend(DREG(insn, 0), OS_BYTE, 0); + dest = gen_extend(DREG(insn, 9), OS_BYTE, 0); + + bcd_sub(dest, src); + + gen_partset_reg(OS_BYTE, DREG(insn, 9), dest); + + bcd_flags(dest); +} + +DISAS_INSN(sbcd_mem) +{ + TCGv src, dest, addr; + + gen_flush_flags(s); /* !Z is sticky */ + + /* Indirect pre-decrement load (mode 4) */ + + src = gen_ea_mode(env, s, 4, REG(insn, 0), OS_BYTE, + NULL_QREG, NULL, EA_LOADU); + dest = gen_ea_mode(env, s, 4, REG(insn, 9), OS_BYTE, + NULL_QREG, &addr, EA_LOADU); + + bcd_sub(dest, src); + + gen_ea_mode(env, s, 4, REG(insn, 9), OS_BYTE, dest, &addr, EA_STORE); + + bcd_flags(dest); +} + +DISAS_INSN(nbcd) +{ + TCGv src, dest; + TCGv addr; + + gen_flush_flags(s); /* !Z is sticky */ + + SRC_EA(env, src, OS_BYTE, 0, &addr); + + dest = tcg_const_i32(0); + bcd_sub(dest, src); + + DEST_EA(env, insn, OS_BYTE, dest, &addr); + + bcd_flags(dest); + + tcg_temp_free(dest); +} + DISAS_INSN(addsub) { TCGv reg; @@ -3689,6 +3900,7 @@ void register_m68k_insns (CPUM68KState *env) INSN(not, 4600, ff00, M68000); INSN(undef, 46c0, ffc0, M68000); INSN(move_to_sr, 46c0, ffc0, CF_ISA_A); + INSN(nbcd, 4800, ffc0, M68000); INSN(linkl, 4808, fff8, M68000); BASE(pea, 4840, ffc0); BASE(swap, 4840, fff8); @@ -3742,6 +3954,8 @@ void register_m68k_insns (CPUM68KState *env) INSN(mvzs, 7100, f100, CF_ISA_B); BASE(or, 8000, f000); BASE(divw, 80c0, f0c0); + INSN(sbcd_reg, 8100, f1f8, M68000); + INSN(sbcd_mem, 8108, f1f8, M68000); BASE(addsub, 9000, f000); INSN(undef, 90c0, f0c0, CF_ISA_A); INSN(subx_reg, 9180, f1f8, CF_ISA_A); @@ -3779,6 +3993,8 @@ void register_m68k_insns (CPUM68KState *env) INSN(exg_aa, c148, f1f8, M68000); INSN(exg_da, c188, f1f8, M68000); BASE(mulw, c0c0, f0c0); + INSN(abcd_reg, c100, f1f8, M68000); + INSN(abcd_mem, c108, f1f8, M68000); BASE(addsub, d000, f000); INSN(undef, d0c0, f0c0, CF_ISA_A); INSN(addx_reg, d180, f1f8, CF_ISA_A);