@@ -411,6 +411,16 @@ static void ppc_powernv_init(MachineState *machine)
}
}
+ /* Create XICS which holds all the ICPs for each thread */
+ object_initialize(&pnv->xics, sizeof(pnv->xics), TYPE_XICS_COMMON);
+ object_property_add_child(OBJECT(machine), "xics", OBJECT(&pnv->xics),
+ &error_fatal);
+ qdev_set_parent_bus(DEVICE(&pnv->xics), sysbus_get_default());
+ object_property_set_int(OBJECT(&pnv->xics), smp_cores * smp_threads,
+ "nr_servers", &error_fatal);
+ object_property_set_bool(OBJECT(&pnv->xics), true, "realized",
+ &error_fatal);
+
/* We need some cpu model to instantiate the PnvChip class */
if (machine->cpu_model == NULL) {
machine->cpu_model = "POWER8";
@@ -22,6 +22,7 @@
#include "hw/boards.h"
#include "hw/sysbus.h"
#include "hw/ppc/pnv_lpc.h"
+#include "hw/ppc/xics.h"
#define TYPE_PNV_CHIP "powernv-chip"
#define PNV_CHIP(obj) OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP)
@@ -113,6 +114,8 @@ typedef struct PnvMachineState {
PnvChip **chips;
ISABus *isa_bus;
+
+ XICSState xics;
} PnvMachineState;
#define PNV_FDT_ADDR 0x01000000
Nothing more than a simple container object for the ICP and ICS. ICPs are still created by the XICS object for the moment. Signed-off-by: Cédric Le Goater <clg@kaod.org> --- David, Please note the qdev_set_parent_bus(). That is how the reset should be handled. I had done that before for the Aspeed SoC machine but I had forgotten ... hw/ppc/pnv.c | 10 ++++++++++ include/hw/ppc/pnv.h | 3 +++ 2 files changed, 13 insertions(+)