From patchwork Mon Nov 7 17:59:21 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Laurent Vivier X-Patchwork-Id: 692016 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3tCKxZ0vs8z9svs for ; Tue, 8 Nov 2016 05:01:06 +1100 (AEDT) Received: from localhost ([::1]:55686 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1c3oEA-0005CS-LT for incoming@patchwork.ozlabs.org; Mon, 07 Nov 2016 13:01:02 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:55849) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1c3oCu-00046j-J4 for qemu-devel@nongnu.org; Mon, 07 Nov 2016 12:59:46 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1c3oCq-0001Xe-8o for qemu-devel@nongnu.org; Mon, 07 Nov 2016 12:59:44 -0500 Received: from mout.kundenserver.de ([212.227.17.24]:58647) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1c3oCp-0001XS-U7 for qemu-devel@nongnu.org; Mon, 07 Nov 2016 12:59:40 -0500 Received: from Quad.localdomain ([78.238.229.36]) by mrelayeu.kundenserver.de (mreue101) with ESMTPSA (Nemesis) id 0MOAtg-1c9KVX49jg-005bLS; Mon, 07 Nov 2016 18:59:28 +0100 From: Laurent Vivier To: qemu-devel@nongnu.org Date: Mon, 7 Nov 2016 18:59:21 +0100 Message-Id: <1478541561-16718-3-git-send-email-laurent@vivier.eu> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1478541561-16718-1-git-send-email-laurent@vivier.eu> References: <1478541561-16718-1-git-send-email-laurent@vivier.eu> X-Provags-ID: V03:K0:VO3a4r1gpAf6Hd2l1L6EbgpCiNSZ8EOCgjdkOliv3wGvN/8pfkN DqSWSZl3WcLXxgAHNUqFy6J3wq1jvrx4BYjxEVGGWJn+iEX0XAWIDJCW99aMD5nmfFjrW// CBnoT9sSmcKDrWG9mLudp+uyi7UTBaRfo/0Csjs33Y8ZGiTg3l89TG4SOHpvOXr3l+n+699 VH98B9VPdjkNl9OG4/+tg== X-UI-Out-Filterresults: notjunk:1; V01:K0:kDSykQt+sV0=:ajFSYqB1CiYa5BUiiarw0r jSztXYXf6mZyN0zu3r0xg/eei1qEnAvi9FwKUkKX4O7cp9DnHtR7LnO6IepKDdXoV1GO3Ffbf gvNK4VyQTDXcW1wdGk1Ybrkq52ALKD8x2mpch32QG13Rgs5PgMjbkXRzaffOb0kHSqCmAnYrc OXVfu3Rysudla+7jnNzPQ9uRZWoD96oPN7mJZwOIoOO1F2mvAceDo1kGy5wsbe1TeE9G0xB9J neHEk0QDkd8j44Z/mTC24Bw8/jRWrPXxLRUmrSe+z78qjOQWn2bj4tGL3R+tV44Lj/Wto8U7O UzZK73U3lS9vH+rEEoK92BRuh/mZmdeu776pVokdRYcSVu40ZHqA0wHUGXHphL6TwNuRnB4V7 N2RBOCsIt0mzE6O2MHWjUrl7V2Qp4PIzmA3LwPr11k9QZhdpNj0MTkXy6NS5aLGyVwPY+1hO2 bugN11R0keFj+kniHPwDo3h7urzDLyPSpmwqd+2AcxLQqAfBEFGAw4wn0LGTvuyLwhHus7B2B Es7AsP3jOjMjaSakMW4dlRhWHbujM8Am87p7tR/gpgPS8kbOULJnAxUdtVP5C/AsLCijGj8cA 4Qxuro/xByf4ZFvHxJDamoMhs/vJBWxbJsREUzlWeRSgeAWnRU0Uo/aXLHHrNoAhskhJRLoqH 3VFhTi7z1h7nvl1kLwl4GG1CrdhYKcacOQxYVfLVQhdJ0UH0GfOi5xtO8ScalJRhrw8U= X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 212.227.17.24 Subject: [Qemu-devel] [PATCH v3 2/2] target-m68k: add cas/cas2 ops X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Laurent Vivier , gerg@uclinux.org, schwab@linux-m68k.org, agraf@suse.de, Richard Henderson Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Implement CAS using cmpxchg. Implement CAS2 using helper and either cmpxchg when the 32bit addresses are consecutive, or with parallel_cpus+cpu_loop_exit_atomic() otherwise. Suggested-by: Richard Henderson Signed-off-by: Laurent Vivier --- target-m68k/helper.h | 2 + target-m68k/op_helper.c | 136 +++++++++++++++++++++++++++++++++++++++++++ target-m68k/translate.c | 151 ++++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 289 insertions(+) diff --git a/target-m68k/helper.h b/target-m68k/helper.h index d863e55..17ec342 100644 --- a/target-m68k/helper.h +++ b/target-m68k/helper.h @@ -9,6 +9,8 @@ DEF_HELPER_4(divull, void, env, int, int, i32) DEF_HELPER_4(divsll, void, env, int, int, s32) DEF_HELPER_2(set_sr, void, env, i32) DEF_HELPER_3(movec, void, env, i32, i32) +DEF_HELPER_4(cas2w, void, env, i32, i32, i32) +DEF_HELPER_4(cas2l, void, env, i32, i32, i32) DEF_HELPER_2(f64_to_i32, f32, env, f64) DEF_HELPER_2(f64_to_f32, f32, env, f64) diff --git a/target-m68k/op_helper.c b/target-m68k/op_helper.c index a4bfa4e..4172ef6 100644 --- a/target-m68k/op_helper.c +++ b/target-m68k/op_helper.c @@ -359,3 +359,139 @@ void HELPER(divsll)(CPUM68KState *env, int numr, int regr, int32_t den) env->dregs[regr] = rem; env->dregs[numr] = quot; } + +void HELPER(cas2w)(CPUM68KState *env, uint32_t regs, uint32_t a1, uint32_t a2) +{ + uint32_t Dc1 = extract32(regs, 9, 3); + uint32_t Dc2 = extract32(regs, 6, 3); + uint32_t Du1 = extract32(regs, 3, 3); + uint32_t Du2 = extract32(regs, 0, 3); + int16_t c1 = env->dregs[Dc1]; + int16_t c2 = env->dregs[Dc2]; + int16_t u1 = env->dregs[Du1]; + int16_t u2 = env->dregs[Du2]; + int16_t l1, l2; + uintptr_t ra = GETPC(); + + if (parallel_cpus) { + /* Tell the main loop we need to serialize this insn. */ + cpu_loop_exit_atomic(ENV_GET_CPU(env), ra); + } else { + /* We're executing in a serial context -- no need to be atomic. */ +#ifdef CONFIG_USER_ONLY + int16_t *ha1 = g2h(a1); + int16_t *ha2 = g2h(a2); + l1 = lduw_be_p(ha1); + l2 = lduw_be_p(ha2); + if (l1 == c1 && l2 == c2) { + stw_be_p(ha1, u1); + stw_be_p(ha2, u2); + } +#else + int mmu_idx = cpu_mmu_index(env, 0); + TCGMemOpIdx oi = make_memop_idx(MO_BESW, mmu_idx); + l1 = helper_be_lduw_mmu(env, a1, oi, ra); + l2 = helper_be_lduw_mmu(env, a2, oi, ra); + if (l1 == c1 && l2 == c2) { + helper_be_stw_mmu(env, a1, u1, oi, ra); + helper_be_stw_mmu(env, a2, u2, oi, ra); + } +#endif + } + + if (c1 != l1) { + env->cc_n = l1; + env->cc_v = c1; + } else { + env->cc_n = l2; + env->cc_v = c2; + } + env->cc_op = CC_OP_CMPW; + env->dregs[Dc1] = deposit32(env->dregs[Dc1], 0, 16, l1); + env->dregs[Dc2] = deposit32(env->dregs[Dc2], 0, 16, l2); +} + +void HELPER(cas2l)(CPUM68KState *env, uint32_t regs, uint32_t a1, uint32_t a2) +{ + uint32_t Dc1 = extract32(regs, 9, 3); + uint32_t Dc2 = extract32(regs, 6, 3); + uint32_t Du1 = extract32(regs, 3, 3); + uint32_t Du2 = extract32(regs, 0, 3); + uint32_t c1 = env->dregs[Dc1]; + uint32_t c2 = env->dregs[Dc2]; + uint32_t u1 = env->dregs[Du1]; + uint32_t u2 = env->dregs[Du2]; + uint32_t l1, l2; + uint64_t c, u, l; + uintptr_t ra = GETPC(); +#ifndef CONFIG_USER_ONLY + int mmu_idx = cpu_mmu_index(env, 0); + TCGMemOpIdx oi; +#endif + + if (parallel_cpus) { + /* We're executing in a parallel context -- must be atomic. */ +#ifdef CONFIG_ATOMIC64 + if ((a1 & 7) == 0 && a2 == a1 + 4) { + c = deposit64(c2, 32, 32, c1); + u = deposit64(u2, 32, 32, u1); +#ifdef CONFIG_USER_ONLY + uint64_t *ha1 = g2h(a1); + l = atomic_cmpxchg__nocheck(ha1, c, u); +#else + oi = make_memop_idx(MO_BEQ, mmu_idx); + l = helper_atomic_cmpxchgq_be_mmu(env, a1, c, u, oi, ra); +#endif + l1 = l >> 32; + l2 = l; + } else if ((a2 & 7) == 0 && a1 == a2 + 4) { + c = deposit64(c1, 32, 32, c2); + u = deposit64(u1, 32, 32, u2); +#ifdef CONFIG_USER_ONLY + uint64_t *ha1 = g2h(a1); + l = atomic_cmpxchg__nocheck(ha1, c, u); +#else + oi = make_memop_idx(MO_BEQ, mmu_idx); + l = helper_atomic_cmpxchgq_be_mmu(env, a1, c, u, oi, ra); +#endif + l2 = l >> 32; + l1 = l; + } else +#endif + { + /* Tell the main loop we need to serialize this insn. */ + cpu_loop_exit_atomic(ENV_GET_CPU(env), ra); + } + } else { +#ifdef CONFIG_USER_ONLY + uint32_t *ha1 = g2h(a1); + uint32_t *ha2 = g2h(a2); + l1 = ldl_be_p(ha1); + l2 = ldl_be_p(ha2); + if (l1 == c1 && l2 == c2) { + stl_be_p(ha1, u1); + stl_be_p(ha2, u2); + } +#else + /* We're executing in a serial context -- no need to be atomic. */ + oi = make_memop_idx(MO_BEUL, mmu_idx); + l1 = helper_be_ldul_mmu(env, a1, oi, ra); + l2 = helper_be_ldul_mmu(env, a2, oi, ra); + if (l1 == c1 && l2 == c2) { + helper_be_stl_mmu(env, a1, u1, oi, ra); + helper_be_stl_mmu(env, a2, u2, oi, ra); + } +#endif + } + + if (c1 != l1) { + env->cc_n = l1; + env->cc_v = c1; + } else { + env->cc_n = l2; + env->cc_v = c2; + } + env->cc_op = CC_OP_CMPL; + env->dregs[Dc1] = l1; + env->dregs[Dc2] = l2; +} diff --git a/target-m68k/translate.c b/target-m68k/translate.c index f3b579a..b9e8e6c 100644 --- a/target-m68k/translate.c +++ b/target-m68k/translate.c @@ -1879,6 +1879,154 @@ DISAS_INSN(arith_im) tcg_temp_free(dest); } +DISAS_INSN(cas) +{ + int opsize; + TCGv addr; + uint16_t ext; + TCGv load; + TCGv cmp; + TCGMemOp opc; + + switch ((insn >> 9) & 3) { + case 1: + opsize = OS_BYTE; + opc = MO_UB; + break; + case 2: + opsize = OS_WORD; + opc = MO_TEUW; + break; + case 3: + opsize = OS_LONG; + opc = MO_TEUL; + break; + default: + g_assert_not_reached(); + } + opc |= MO_ALIGN; + + ext = read_im16(env, s); + + /* cas Dc,Du, */ + + addr = gen_lea(env, s, insn, opsize); + if (IS_NULL_QREG(addr)) { + gen_addr_fault(s); + return; + } + + cmp = gen_extend(DREG(ext, 0), opsize, 0); + + /* if == Dc then + * = Du + * Dc = (because == Dc) + * else + * Dc = + */ + + load = tcg_temp_new(); + tcg_gen_atomic_cmpxchg_i32(load, addr, cmp, DREG(ext, 6), + IS_USER(s), opc); + gen_partset_reg(opsize, DREG(ext, 0), load); + + gen_update_cc_cmp(s, load, cmp, opsize); + tcg_temp_free(load); +} + +DISAS_INSN(cas2w) +{ + uint16_t ext1, ext2; + TCGv addr1, addr2; + TCGv regs; + + /* cas2 Dc1:Dc2,Du1:Du2,(Rn1):(Rn2) */ + + ext1 = read_im16(env, s); + + if (ext1 & 0x8000) { + /* Address Register */ + addr1 = AREG(ext1, 12); + } else { + /* Data Register */ + addr1 = DREG(ext1, 12); + } + + ext2 = read_im16(env, s); + if (ext2 & 0x8000) { + /* Address Register */ + addr2 = AREG(ext2, 12); + } else { + /* Data Register */ + addr2 = DREG(ext2, 12); + } + + /* if (R1) == Dc1 && (R2) == Dc2 then + * (R1) = Du1 + * (R2) = Du2 + * else + * Dc1 = (R1) + * Dc2 = (R2) + */ + + regs = tcg_const_i32(REG(ext2, 6) | + (REG(ext1, 6) << 3) | + (REG(ext2, 0) << 6) | + (REG(ext1, 0) << 9)); + gen_helper_cas2w(cpu_env, regs, addr1, addr2); + tcg_temp_free(regs); + + /* Note that cas2w also assigned to env->cc_op. */ + s->cc_op = CC_OP_CMPW; + s->cc_op_synced = 1; +} + +DISAS_INSN(cas2l) +{ + uint16_t ext1, ext2; + TCGv addr1, addr2, regs; + + /* cas2 Dc1:Dc2,Du1:Du2,(Rn1):(Rn2) */ + + ext1 = read_im16(env, s); + + if (ext1 & 0x8000) { + /* Address Register */ + addr1 = AREG(ext1, 12); + } else { + /* Data Register */ + addr1 = DREG(ext1, 12); + } + + ext2 = read_im16(env, s); + if (ext2 & 0x8000) { + /* Address Register */ + addr2 = AREG(ext2, 12); + } else { + /* Data Register */ + addr2 = DREG(ext2, 12); + } + + /* if (R1) == Dc1 && (R2) == Dc2 then + * (R1) = Du1 + * (R2) = Du2 + * else + * Dc1 = (R1) + * Dc2 = (R2) + */ + + regs = tcg_const_i32(REG(ext2, 6) | + (REG(ext1, 6) << 3) | + (REG(ext2, 0) << 6) | + (REG(ext1, 0) << 9)); + gen_helper_cas2l(cpu_env, regs, addr1, addr2); + tcg_temp_free(regs); + + /* Note that cas2l also assigned to env->cc_op. */ + s->cc_op = CC_OP_CMPL; + s->cc_op_synced = 1; +} + DISAS_INSN(byterev) { TCGv reg; @@ -3873,6 +4021,9 @@ void register_m68k_insns (CPUM68KState *env) INSN(arith_im, 0680, fff8, CF_ISA_A); INSN(arith_im, 0c00, ff38, CF_ISA_A); INSN(arith_im, 0c00, ff00, M68000); + INSN(cas, 08c0, f9c0, CAS); + INSN(cas2w, 0cfc, ffff, CAS); + INSN(cas2l, 0efc, ffff, CAS); BASE(bitop_im, 0800, ffc0); BASE(bitop_im, 0840, ffc0); BASE(bitop_im, 0880, ffc0);