From patchwork Thu Nov 3 14:07:48 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Laurent Vivier X-Patchwork-Id: 690873 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3t8mzw21ssz9vFB for ; Fri, 4 Nov 2016 01:09:15 +1100 (AEDT) Received: from localhost ([::1]:33270 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1c2Ihb-0003j5-TK for incoming@patchwork.ozlabs.org; Thu, 03 Nov 2016 10:09:11 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:33074) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1c2Igq-0003RM-KW for qemu-devel@nongnu.org; Thu, 03 Nov 2016 10:08:32 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1c2Igl-0002ZE-LW for qemu-devel@nongnu.org; Thu, 03 Nov 2016 10:08:24 -0400 Received: from mout.kundenserver.de ([217.72.192.75]:56926) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1c2Igl-0002Ys-CM for qemu-devel@nongnu.org; Thu, 03 Nov 2016 10:08:19 -0400 Received: from Quad.localdomain ([78.238.229.36]) by mrelayeu.kundenserver.de (mreue101) with ESMTPSA (Nemesis) id 0MVLtW-1cMdda1syc-00YhZx; Thu, 03 Nov 2016 15:07:56 +0100 From: Laurent Vivier To: Aurelien Jarno Date: Thu, 3 Nov 2016 15:07:48 +0100 Message-Id: <1478182068-14082-1-git-send-email-laurent@vivier.eu> X-Mailer: git-send-email 2.7.4 X-Provags-ID: V03:K0:xqg5MOwd60JqLs8MLfYxHKlz0Zoi1o5x5CCVaS5SGKkzL3jaQl8 E4LUd+cTXVkgG9qZUM0HFNKYRG7YEERQi/WNlneM7AKp8vK5Qt6E+QQar48sfug4q4j7mOK WBu76DXRzq9toe8k4sJ3pUl4vKNzjh1IHoj4nDW6FmkRPj5zXz08ahZ2PVgN116gfMJ14Za hhY7V0YCxq52V3+iRkiRg== X-UI-Out-Filterresults: notjunk:1; V01:K0:Q8ip10JJB9c=:DNAWpdjLGYz4YwcqpaJfZn 1AmvtmMZr4B8JrTDLkNP4vBaK0ETV71N6EtzKs6f3xWs1Niqgtrk7kRsIBwNSDZeb1Iwc++mG JcDOksMFOlPd41iM6qkJ0NWRRZWU3LF6rM1ZCWnPR+VP+lV+sTq+JLmS6c1lDdgKhTu5ycxsL nUgzB+CLQwAOPKqawjDgPhqXiNTnsIIe9W1RsPJwt8CTn52xv2KSb9m6ExX9da6Nqf8eLsOdk IyZVSQy1FrkeEVeE37iRzOtjUPqAenx++IJLi7QS2qa/1m6HE6ie1ZYe5YdAhQXBmZEoiZEez KwHDdGmVAbgVHFqAbD80KlresVFtJCC4YA8RIQ2SdkRw46ZVteSjXauxHq0VzskQNCzq+QEpQ 7Qh+1ukuuvvShSdNDaCCXF2uXQN7UvhkmNxdmqjFq8hd88247CkwfMhypqzGPUiUQUY2z3X9Z 4Gb5PWQdWOaT/5Whq+SUev9yIewlStgISkNuJDEOJ/Q9pLDtEi5PnTs1+AfbX3P8KvaTThrni 2rPs99Vtali/ob6mCHDo7k5994IcJ4Jxm6/ax8orGzSvv05eLix3Fw0PcmnoFGe1foUuAv2Fw 4x6zglVm6crBgVWp7n3xdj1e41BH9sWlvGb7BkryNI72LtYxW803JYjox4ZDD1RbBABaMyh+o aSlOsXGVFWfs4yuAT0wohhOF9QXP/3ruaD+ZR8LFarXPmcP/aEbhuQTxBVJAhgPaymO8= X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 217.72.192.75 Subject: [Qemu-devel] [PATCH v2] target-sh4: add atomic tas X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Paolo Bonzini , John Paul Adrian Glaubitz , Laurent Vivier , qemu-devel@nongnu.org, Richard Henderson Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Implement real atomic tas: When (Rn) = 0, 1 -> T Otherwise, 0 -> T In both cases, 1 -> MSB of (Rn) using atomic_fetch_or_i32() and setcondi_i32(). Tested with image from: http://wiki.qemu.org/download/sh-test-0.2.tar.bz2 This image contains a "tas_test" that runs without error with this change. Signed-off-by: Laurent Vivier Reviewed-by: Richard Henderson Reviewed-by: Aurelien Jarno Acked-by: Aurelien Jarno --- v2: - don't use helper but atomic_fetch_or_i32 Thank you Paolo! target-sh4/translate.c | 19 ++++++++----------- 1 file changed, 8 insertions(+), 11 deletions(-) diff --git a/target-sh4/translate.c b/target-sh4/translate.c index c89a147..1b83d59 100644 --- a/target-sh4/translate.c +++ b/target-sh4/translate.c @@ -1640,18 +1640,15 @@ static void _decode_opc(DisasContext * ctx) tcg_gen_shri_i32(REG(B11_8), REG(B11_8), 16); return; case 0x401b: /* tas.b @Rn */ - { - TCGv addr, val; - addr = tcg_temp_local_new(); - tcg_gen_mov_i32(addr, REG(B11_8)); - val = tcg_temp_local_new(); - tcg_gen_qemu_ld_i32(val, addr, ctx->memidx, MO_UB); + { + TCGv val = tcg_temp_new(); + TCGv msb = tcg_const_i32(0x80); + tcg_gen_atomic_fetch_or_i32(val, REG(B11_8), msb, + ctx->memidx, MO_UB); + tcg_temp_free(msb); tcg_gen_setcondi_i32(TCG_COND_EQ, cpu_sr_t, val, 0); - tcg_gen_ori_i32(val, val, 0x80); - tcg_gen_qemu_st_i32(val, addr, ctx->memidx, MO_UB); - tcg_temp_free(val); - tcg_temp_free(addr); - } + tcg_temp_free(val); + } return; case 0xf00d: /* fsts FPUL,FRn - FPSCR: Nothing */ CHECK_FPU_ENABLED