From patchwork Wed Nov 2 21:15:18 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Laurent Vivier X-Patchwork-Id: 690603 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3t8LY02qMJz9tlB for ; Thu, 3 Nov 2016 08:17:56 +1100 (AEDT) Received: from localhost ([::1]:57785 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1c22uw-000863-84 for incoming@patchwork.ozlabs.org; Wed, 02 Nov 2016 17:17:54 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38617) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1c22so-0006Wz-7L for qemu-devel@nongnu.org; Wed, 02 Nov 2016 17:15:46 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1c22sj-00049D-NW for qemu-devel@nongnu.org; Wed, 02 Nov 2016 17:15:42 -0400 Received: from mout.kundenserver.de ([212.227.17.13]:50249) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1c22sj-00048g-E5 for qemu-devel@nongnu.org; Wed, 02 Nov 2016 17:15:37 -0400 Received: from Quad.localdomain ([78.238.229.36]) by mrelayeu.kundenserver.de (mreue102) with ESMTPSA (Nemesis) id 0MPGtM-1bxd2F1Rdw-004SPE; Wed, 02 Nov 2016 22:15:27 +0100 From: Laurent Vivier To: qemu-devel@nongnu.org Date: Wed, 2 Nov 2016 22:15:18 +0100 Message-Id: <1478121319-31986-3-git-send-email-laurent@vivier.eu> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1478121319-31986-1-git-send-email-laurent@vivier.eu> References: <1478121319-31986-1-git-send-email-laurent@vivier.eu> X-Provags-ID: V03:K0:jwjPy0Bc+XnYY+Wor+Q+l+Olra9M8OjQ9/RNDkiaPKJbLTwzRlz ZKGGjuU83r04RgMgHR1Z7IkY0R0PAfOqzTCxIt43dbk8lkMpYaNmX4BcrHoYom3oktDpQjv C5So59yBZPW9VQ5Yqu/Ckh8pMHWdzIU5/wSq0//CZLdfXdaSvaQocXSFKFiFQIlSLisdaJl +N2gLuxlP00DmtJiTYaFg== X-UI-Out-Filterresults: notjunk:1; V01:K0:v+UqaB+93t0=:pO8U+iV/CDUSAzJDUwa57V rXOLWQmXFQzh0dnWpZqhbRddqRsqOeTAah3VQquCaBzNaolHajbXnFkh9hnK9UNUNU5a0rc+b 3YMK0pDOF0QIWSKG6ODuZ/NlRO9uwTfwSX8HvsWvA0yfaEPvqMtjOdIvvfIhxl1VJmWG7pbzZ MJKr0qiPVMY9rPq6puEIx2SddTJZRuIBQuLofQT5hU8PcmThd8RQBsjsJqBRlInrV60i4ScEO PcsvBbG3cbtlxP9T82iWIo4YlRikaf1BRnt6TsMlNk58mBzlm4TX0k3hvqngKVNrPP++fPFJX 2OK1h4z5a9bVXBlImlFkjy+7J2QY2Qo+oDG3cJT9KzjzIJpe9bClt+g5UtNaIGMd81NMUj7xp HKd8jaCsB6ej21TentCBUjCD8pFXbXbw44/RT6FXpTbLipbPXCupEQFqWIsaQYBX30dkpKxuS R0O6MWEOrioGOWMahleWX/xwkDDlKZW1Z+m7Mud24FpzYdZID+eUMHd+pzE/eIbEH4q5RbHEP C/0N5QxX6V300OHI4p+WmAnnfh8XHK7o3ws81yx6UM5fAkqPfbgAnuro3Ni3COxPVnJA6MZll L1FkcirSDa6phDLzGJbFODU88/mPURsKQdiWym/EOl40v9gYrful7pOgx3F7NeIQAoiWaM/Xq C177IDzAmjzt3OYrH20ZgxjelrY2R1xvEVHxjuumvaWaAgJmHhRealwlWa+tlwat8Mo0= X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 212.227.17.13 Subject: [Qemu-devel] [PATCH v2 2/3] target-m68k: implement 680x0 movem X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Laurent Vivier , gerg@uclinux.org, schwab@linux-m68k.org, agraf@suse.de, Richard Henderson Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" 680x0 movem can load/store words and long words and can use more addressing modes. Coldfire can only use long words with (Ax) and (d16,Ax) addressing modes. Signed-off-by: Laurent Vivier Reviewed-by: Richard Henderson --- target-m68k/translate.c | 96 ++++++++++++++++++++++++++++++++++++++++--------- 1 file changed, 79 insertions(+), 17 deletions(-) diff --git a/target-m68k/translate.c b/target-m68k/translate.c index 1cf88a4..93f1270 100644 --- a/target-m68k/translate.c +++ b/target-m68k/translate.c @@ -1667,14 +1667,25 @@ static void gen_push(DisasContext *s, TCGv val) tcg_gen_mov_i32(QREG_SP, tmp); } +static TCGv mreg(int reg) +{ + if (reg < 8) { + /* Dx */ + return cpu_dregs[reg]; + } + /* Ax */ + return cpu_aregs[reg & 7]; +} + DISAS_INSN(movem) { TCGv addr; int i; uint16_t mask; - TCGv reg; TCGv tmp; - int is_load; + int is_load = (insn & 0x0400) != 0; + int opsize = (insn & 0x40) != 0 ? OS_LONG : OS_WORD; + TCGv incr; mask = read_im16(env, s); tmp = gen_lea(env, s, insn, OS_LONG); @@ -1682,25 +1693,74 @@ DISAS_INSN(movem) gen_addr_fault(s); return; } + addr = tcg_temp_new(); tcg_gen_mov_i32(addr, tmp); - is_load = ((insn & 0x0400) != 0); - for (i = 0; i < 16; i++, mask >>= 1) { - if (mask & 1) { - if (i < 8) - reg = DREG(i, 0); - else - reg = AREG(i, 0); - if (is_load) { - tmp = gen_load(s, OS_LONG, addr, 0); - tcg_gen_mov_i32(reg, tmp); - } else { - gen_store(s, OS_LONG, addr, reg); + incr = tcg_const_i32(opsize_bytes(opsize)); + + if (is_load) { + /* memory to register */ + TCGv r[16]; + for (i = 0; i < 16; i++) { + if ((mask >> i) & 1) { + r[i] = gen_load(s, opsize, addr, 1); + tcg_gen_add_i32(addr, addr, incr); + } + } + for (i = 0; i < 16; i++, mask >>= 1) { + if (mask & 1) { + tcg_gen_mov_i32(mreg(i), r[i]); + tcg_temp_free(r[i]); + } + } + if ((insn & 070) == 030) { + /* movem (An)+,X */ + tcg_gen_mov_i32(AREG(insn, 0), addr); + } + + } else { + /* register to memory */ + + if ((insn & 070) == 040) { + /* movem X,-(An) */ + + for (i = 15; i >= 0; i--, mask >>= 1) { + if (mask & 1) { + if ((insn & 7) + 8 == i && + m68k_feature(s->env, M68K_FEATURE_EXT_FULL)) { + /* M68020+: if the addressing register is the + * register moved to memory, the value written + * is the initial value decremented by the size of + * the operation + * M68000/M68010: the value is the initial value + */ + TCGv tmp = tcg_temp_new(); + tcg_gen_sub_i32(tmp, mreg(i), incr); + gen_store(s, opsize, addr, tmp); + tcg_temp_free(tmp); + } else { + gen_store(s, opsize, addr, mreg(i)); + } + if (mask != 1) { + tcg_gen_sub_i32(addr, addr, incr); + } + } + } + tcg_gen_mov_i32(AREG(insn, 0), addr); + } else { + /* movem X,(An)+ is not allowed */ + + for (i = 0; i < 16; i++, mask >>= 1) { + if (mask & 1) { + gen_store(s, opsize, addr, mreg(i)); + tcg_gen_add_i32(addr, addr, incr); + } } - if (mask != 1) - tcg_gen_addi_i32(addr, addr, 4); } } + + tcg_temp_free(incr); + tcg_temp_free(addr); } DISAS_INSN(bitop_im) @@ -3858,7 +3918,9 @@ void register_m68k_insns (CPUM68KState *env) BASE(pea, 4840, ffc0); BASE(swap, 4840, fff8); INSN(bkpt, 4848, fff8, BKPT); - BASE(movem, 48c0, fbc0); + INSN(movem, 48d0, fbf8, CF_ISA_A); + INSN(movem, 48e8, fbf8, CF_ISA_A); + INSN(movem, 4880, fb80, M68000); BASE(ext, 4880, fff8); BASE(ext, 48c0, fff8); BASE(ext, 49c0, fff8);