From patchwork Mon Oct 31 23:48:12 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Laurent Vivier X-Patchwork-Id: 689702 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3t7B4Q6s1Mz9t0t for ; Tue, 1 Nov 2016 10:52:38 +1100 (AEDT) Received: from localhost ([::1]:39105 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1c1MNY-0002V4-Bb for incoming@patchwork.ozlabs.org; Mon, 31 Oct 2016 19:52:36 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:41915) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1c1MJg-0008MG-M7 for qemu-devel@nongnu.org; Mon, 31 Oct 2016 19:48:38 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1c1MJe-00072I-QK for qemu-devel@nongnu.org; Mon, 31 Oct 2016 19:48:36 -0400 Received: from mout.kundenserver.de ([212.227.17.10]:58091) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1c1MJe-00071Z-Fz for qemu-devel@nongnu.org; Mon, 31 Oct 2016 19:48:34 -0400 Received: from Quad.localdomain ([78.238.229.36]) by mrelayeu.kundenserver.de (mreue103) with ESMTPSA (Nemesis) id 0MbK2G-1cHnEX1a7A-00Imi9; Tue, 01 Nov 2016 00:48:21 +0100 From: Laurent Vivier To: qemu-devel@nongnu.org Date: Tue, 1 Nov 2016 00:48:12 +0100 Message-Id: <1477957692-7231-3-git-send-email-laurent@vivier.eu> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1477957692-7231-1-git-send-email-laurent@vivier.eu> References: <1477957692-7231-1-git-send-email-laurent@vivier.eu> X-Provags-ID: V03:K0:6CNmHD8Thnp7AYsjawY3EAv0fgYCBXKOYKMafbeKz+0PtqfOkFV W+GPKjdbo+kwSpC5A4ZSynzfqM+OFOYG+xgnAtYWhIkZhGkKZ34ff62TtdE4ixMFQWTMazD dog+txX09P4Dhhfah9Jz6tfxiPm4tz9dbQipF8N8BCmHeMxHJjh3yIR85f7DXkxt3LcpOlM PLNVL4+SfX1BAJMlOBxWQ== X-UI-Out-Filterresults: notjunk:1; V01:K0:icDQVw/XR6g=:zq1y70b+zbFRZoJFUWbQ6/ FfvdYSXfbCwxpcC/hEdsk04JB78xe8Cg59F0PGQW/GDuOsrPptmaNO5l74q2byt5D221ynCz4 7o1Ytct0upA32I4TsmzK8+lp67xhW1ufvjZfOoUh8W57BjM2EnYfYEWeGYLTgFMyVz5PbP/ET UcFYvgAd+UF8ngaxfXXrUFRCn86RhY+5b2uJLMZCRtrj85Yf+Gzs60HJbq+r3PSwqaU5YxJ2A B6WHTyjrhZyKyHkXVKJMymLTSbAWvXynuGq8rEy0vODWB7l/ATKxtV8aIM+g9h+dQJpxKhOu+ GdoeaeejJ/gNvUY2YXnphJC9kyjABzCBCGoBNiLvSmq0CE+Q2vfXV9gRqEyHINbeXnTocX/rH PEhS3KDLFVvNAN4WOb4x/z2q9qX9aB4KoynBHetxJ3bhsANsMYftNRZvt0SddCgumb/CEYd1N 5FqkX6x/ZJMHbI6Wp0QfMQOamC9TtXc/6DgH83CLgrbXm5xWMzRCMcHMXrrx8GCPniNr0UcE6 ZgEFsz/cs64ttEGQEImouH8NAngxP8UuG0iMpa/8Sw6nw/CZrjNcxZGWOph7E7BG5rU2Ytxch He0S0b8BbG3vjEKIThvce8E+Br58l6epMqbA5G0LhF5FJVicCkkir59wY4C79Nq9yH16FaK8J WGyh5c32Xg0MOqwSfJVr0xsMLM7CzWuz24Rw7bWVTtw+lsjh4S6VfPlSvelO3T6PXz1s= X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 212.227.17.10 Subject: [Qemu-devel] [PATCH v3 2/2] target-m68k: add 680x0 divu/divs variants X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Laurent Vivier , gerg@uclinux.org, schwab@linux-m68k.org, agraf@suse.de, Richard Henderson Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Update helper to set the throwing location in case of div-by-0. Cleanup divX.w and add quad word variants of divX.l. Signed-off-by: Laurent Vivier --- linux-user/main.c | 7 ++ target-m68k/cpu.h | 4 -- target-m68k/helper.h | 8 ++- target-m68k/op_helper.c | 182 +++++++++++++++++++++++++++++++++++++++++------- target-m68k/qregs.def | 2 - target-m68k/translate.c | 84 ++++++++++++---------- 6 files changed, 217 insertions(+), 70 deletions(-) diff --git a/linux-user/main.c b/linux-user/main.c index 75b199f..c1d5eb4 100644 --- a/linux-user/main.c +++ b/linux-user/main.c @@ -2864,6 +2864,13 @@ void cpu_loop(CPUM68KState *env) info._sifields._sigfault._addr = env->pc; queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); break; + case EXCP_DIV0: + info.si_signo = TARGET_SIGFPE; + info.si_errno = 0; + info.si_code = TARGET_FPE_INTDIV; + info._sifields._sigfault._addr = env->pc; + queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); + break; case EXCP_TRAP0: { abi_long ret; diff --git a/target-m68k/cpu.h b/target-m68k/cpu.h index 6dfb54e..0b4ed7b 100644 --- a/target-m68k/cpu.h +++ b/target-m68k/cpu.h @@ -95,10 +95,6 @@ typedef struct CPUM68KState { uint32_t macsr; uint32_t mac_mask; - /* Temporary storage for DIV helpers. */ - uint32_t div1; - uint32_t div2; - /* MMU status. */ struct { uint32_t ar; diff --git a/target-m68k/helper.h b/target-m68k/helper.h index aae01f9..d863e55 100644 --- a/target-m68k/helper.h +++ b/target-m68k/helper.h @@ -1,8 +1,12 @@ DEF_HELPER_1(bitrev, i32, i32) DEF_HELPER_1(ff1, i32, i32) DEF_HELPER_FLAGS_2(sats, TCG_CALL_NO_RWG_SE, i32, i32, i32) -DEF_HELPER_2(divu, void, env, i32) -DEF_HELPER_2(divs, void, env, i32) +DEF_HELPER_3(divuw, void, env, int, i32) +DEF_HELPER_3(divsw, void, env, int, s32) +DEF_HELPER_4(divul, void, env, int, int, i32) +DEF_HELPER_4(divsl, void, env, int, int, s32) +DEF_HELPER_4(divull, void, env, int, int, i32) +DEF_HELPER_4(divsll, void, env, int, int, s32) DEF_HELPER_2(set_sr, void, env, i32) DEF_HELPER_3(movec, void, env, i32, i32) diff --git a/target-m68k/op_helper.c b/target-m68k/op_helper.c index 48e02e4..ef0d25d 100644 --- a/target-m68k/op_helper.c +++ b/target-m68k/op_helper.c @@ -166,12 +166,17 @@ bool m68k_cpu_exec_interrupt(CPUState *cs, int interrupt_request) return false; } -static void raise_exception(CPUM68KState *env, int tt) +static void raise_exception_ra(CPUM68KState *env, int tt, uintptr_t raddr) { CPUState *cs = CPU(m68k_env_get_cpu(env)); cs->exception_index = tt; - cpu_loop_exit(cs); + cpu_loop_exit_restore(cs, raddr); +} + +static void raise_exception(CPUM68KState *env, int tt) +{ + raise_exception_ra(env, tt, 0); } void HELPER(raise_exception)(CPUM68KState *env, uint32_t tt) @@ -179,51 +184,178 @@ void HELPER(raise_exception)(CPUM68KState *env, uint32_t tt) raise_exception(env, tt); } -void HELPER(divu)(CPUM68KState *env, uint32_t word) +void HELPER(divuw)(CPUM68KState *env, int destr, uint32_t den) { - uint32_t num; - uint32_t den; - uint32_t quot; - uint32_t rem; + uint32_t num = env->dregs[destr]; + uint32_t quot, rem; - num = env->div1; - den = env->div2; - /* ??? This needs to make sure the throwing location is accurate. */ if (den == 0) { - raise_exception(env, EXCP_DIV0); + raise_exception_ra(env, EXCP_DIV0, GETPC()); } quot = num / den; rem = num % den; - env->cc_v = (word && quot > 0xffff ? -1 : 0); + env->cc_c = 0; /* always cleared, even if overflow */ + if (quot > 0xffff) { + env->cc_v = -1; + /* nothing else is modified */ + /* real 68040 keeps Z and N on overflow, + * whereas documentation says "undefined" + */ + return; + } + env->dregs[destr] = deposit32(quot, 16, 16, rem); env->cc_z = quot; env->cc_n = quot; + env->cc_v = 0; +} + +void HELPER(divsw)(CPUM68KState *env, int destr, int32_t den) +{ + int32_t num = env->dregs[destr]; + uint32_t quot, rem; + + if (den == 0) { + raise_exception_ra(env, EXCP_DIV0, GETPC()); + } + quot = num / den; + rem = num % den; + + env->cc_c = 0; /* always cleared, even if overflow */ + if (quot != (int16_t)quot) { + env->cc_v = -1; + /* nothing else is modified */ + /* real 68040 keeps Z and N on overflow, + * whereas documentation says "undefined" + */ + return; + } + env->dregs[destr] = deposit32(quot, 16, 16, rem); + env->cc_z = quot; + env->cc_n = quot; + env->cc_v = 0; +} + +void HELPER(divul)(CPUM68KState *env, int numr, int regr, uint32_t den) +{ + uint32_t num = env->dregs[numr]; + uint32_t quot, rem; + + if (den == 0) { + raise_exception_ra(env, EXCP_DIV0, GETPC()); + } + quot = num / den; + rem = num % den; + env->cc_c = 0; + env->cc_z = quot; + env->cc_n = quot; + env->cc_v = 0; - env->div1 = quot; - env->div2 = rem; + if (m68k_feature(env, M68K_FEATURE_CF_ISA_A)) { + if (numr == regr) { + env->dregs[numr] = quot; + } else { + env->dregs[regr] = rem; + } + } else { + env->dregs[regr] = rem; + env->dregs[numr] = quot; + } } -void HELPER(divs)(CPUM68KState *env, uint32_t word) +void HELPER(divsl)(CPUM68KState *env, int numr, int regr, int32_t den) { - int32_t num; - int32_t den; - int32_t quot; + int32_t num = env->dregs[numr]; + int32_t quot, rem; + + if (den == 0) { + raise_exception_ra(env, EXCP_DIV0, GETPC()); + } + quot = num / den; + rem = num % den; + + env->cc_c = 0; + env->cc_z = quot; + env->cc_n = quot; + env->cc_v = 0; + + if (m68k_feature(env, M68K_FEATURE_CF_ISA_A)) { + if (numr == regr) { + env->dregs[numr] = quot; + } else { + env->dregs[regr] = rem; + } + } else { + env->dregs[regr] = rem; + env->dregs[numr] = quot; + } +} + +void HELPER(divull)(CPUM68KState *env, int numr, int regr, uint32_t den) +{ + uint32_t num = env->dregs[numr]; + uint64_t quot; + uint32_t rem; + + if (den == 0) { + raise_exception_ra(env, EXCP_DIV0, GETPC()); + } + quot = num / den; + rem = num % den; + + env->cc_c = 0; /* always cleared, even if overflow */ + if (quot > 0xffffffffULL) { + env->cc_v = -1; + /* nothing else is modified */ + /* real 68040 keeps Z and N on overflow, + * whereas documentation says "undefined" + */ + return; + } + env->cc_z = quot; + env->cc_n = quot; + env->cc_v = 0; + + /* + * If Dq and Dr are the same, the quotient is returned. + * therefore we set Dq last. + */ + + env->dregs[regr] = rem; + env->dregs[numr] = quot; +} + +void HELPER(divsll)(CPUM68KState *env, int numr, int regr, int32_t den) +{ + int32_t num = env->dregs[numr]; + int64_t quot; int32_t rem; - num = env->div1; - den = env->div2; if (den == 0) { - raise_exception(env, EXCP_DIV0); + raise_exception_ra(env, EXCP_DIV0, GETPC()); } quot = num / den; rem = num % den; - env->cc_v = (word && quot != (int16_t)quot ? -1 : 0); + env->cc_c = 0; /* always cleared, even if overflow */ + if (!((quot >> 31) == 0 || (quot >> 31) == -1)) { + env->cc_v = -1; + /* nothing else is modified */ + /* real 68040 keeps Z and N on overflow, + * whereas documentation says "undefined" + */ + return; + } env->cc_z = quot; env->cc_n = quot; - env->cc_c = 0; + env->cc_v = 0; + + /* + * If Dq and Dr are the same, the quotient is returned. + * therefore we set Dq last. + */ - env->div1 = quot; - env->div2 = rem; + env->dregs[regr] = rem; + env->dregs[numr] = quot; } diff --git a/target-m68k/qregs.def b/target-m68k/qregs.def index 156c0f5..51ff43b 100644 --- a/target-m68k/qregs.def +++ b/target-m68k/qregs.def @@ -7,7 +7,5 @@ DEFO32(CC_C, cc_c) DEFO32(CC_N, cc_n) DEFO32(CC_V, cc_v) DEFO32(CC_Z, cc_z) -DEFO32(DIV1, div1) -DEFO32(DIV2, div2) DEFO32(MACSR, macsr) DEFO32(MAC_MASK, mac_mask) diff --git a/target-m68k/translate.c b/target-m68k/translate.c index 93e201c..807fe9f 100644 --- a/target-m68k/translate.c +++ b/target-m68k/translate.c @@ -1191,64 +1191,74 @@ DISAS_INSN(mulw) DISAS_INSN(divw) { - TCGv reg; - TCGv tmp; - TCGv src; int sign; + TCGv src; + TCGv destr; + + /* divX.w ,Dn 32/16 -> 16r:16q */ sign = (insn & 0x100) != 0; - reg = DREG(insn, 9); - if (sign) { - tcg_gen_ext16s_i32(QREG_DIV1, reg); - } else { - tcg_gen_ext16u_i32(QREG_DIV1, reg); - } + + /* dest.l / src.w */ + SRC_EA(env, src, OS_WORD, sign, NULL); - tcg_gen_mov_i32(QREG_DIV2, src); + destr = tcg_const_i32(REG(insn, 9)); if (sign) { - gen_helper_divs(cpu_env, tcg_const_i32(1)); + gen_helper_divsw(cpu_env, destr, src); } else { - gen_helper_divu(cpu_env, tcg_const_i32(1)); + gen_helper_divuw(cpu_env, destr, src); } - - tmp = tcg_temp_new(); - src = tcg_temp_new(); - tcg_gen_ext16u_i32(tmp, QREG_DIV1); - tcg_gen_shli_i32(src, QREG_DIV2, 16); - tcg_gen_or_i32(reg, tmp, src); + tcg_temp_free(destr); set_cc_op(s, CC_OP_FLAGS); } DISAS_INSN(divl) { - TCGv num; - TCGv den; - TCGv reg; + TCGv num, reg, den; + int sign; uint16_t ext; ext = read_im16(env, s); - if (ext & 0x87f8) { - gen_exception(s, s->pc - 4, EXCP_UNSUPPORTED); + + sign = (ext & 0x0800) != 0; + + if (ext & 0x400) { + if (!m68k_feature(s->env, M68K_FEATURE_QUAD_MULDIV)) { + gen_exception(s, s->insn_pc, EXCP_ILLEGAL); + return; + } + + /* divX.l , Dr:Dq 64/32 -> 32r:32q */ + + SRC_EA(env, den, OS_LONG, 0, NULL); + num = tcg_const_i32(REG(ext, 12)); + reg = tcg_const_i32(REG(ext, 0)); + if (sign) { + gen_helper_divsll(cpu_env, num, reg, den); + } else { + gen_helper_divull(cpu_env, num, reg, den); + } + tcg_temp_free(reg); + tcg_temp_free(num); + set_cc_op(s, CC_OP_FLAGS); return; } - num = DREG(ext, 12); - reg = DREG(ext, 0); - tcg_gen_mov_i32(QREG_DIV1, num); + + /* divX.l , Dq 32/32 -> 32q */ + /* divXl.l , Dr:Dq 32/32 -> 32r:32q */ + SRC_EA(env, den, OS_LONG, 0, NULL); - tcg_gen_mov_i32(QREG_DIV2, den); - if (ext & 0x0800) { - gen_helper_divs(cpu_env, tcg_const_i32(0)); - } else { - gen_helper_divu(cpu_env, tcg_const_i32(0)); - } - if ((ext & 7) == ((ext >> 12) & 7)) { - /* div */ - tcg_gen_mov_i32 (reg, QREG_DIV1); + num = tcg_const_i32(REG(ext, 12)); + reg = tcg_const_i32(REG(ext, 0)); + if (sign) { + gen_helper_divsl(cpu_env, num, reg, den); } else { - /* rem */ - tcg_gen_mov_i32 (reg, QREG_DIV2); + gen_helper_divul(cpu_env, num, reg, den); } + tcg_temp_free(reg); + tcg_temp_free(num); + set_cc_op(s, CC_OP_FLAGS); }