From patchwork Fri Oct 28 08:48:18 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Laurent Vivier X-Patchwork-Id: 688311 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3t4yjv01S5z9s8x for ; Fri, 28 Oct 2016 20:13:55 +1100 (AEDT) Received: from localhost ([::1]:47663 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1c03EW-0000eu-Jb for incoming@patchwork.ozlabs.org; Fri, 28 Oct 2016 05:13:52 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:41008) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1c02vU-0001bv-Qg for qemu-devel@nongnu.org; Fri, 28 Oct 2016 04:54:13 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1c02vQ-0004pl-QE for qemu-devel@nongnu.org; Fri, 28 Oct 2016 04:54:12 -0400 Received: from mout.kundenserver.de ([212.227.126.130]:59939) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1c02vQ-0004oP-GN for qemu-devel@nongnu.org; Fri, 28 Oct 2016 04:54:08 -0400 Received: from Quad.localdomain ([78.238.229.36]) by mrelayeu.kundenserver.de (mreue002) with ESMTPSA (Nemesis) id 0MeGdC-1cG3nD0L8Q-00PtGV; Fri, 28 Oct 2016 10:48:41 +0200 From: Laurent Vivier To: qemu-devel@nongnu.org Date: Fri, 28 Oct 2016 10:48:18 +0200 Message-Id: <1477644512-21716-5-git-send-email-laurent@vivier.eu> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1477644512-21716-1-git-send-email-laurent@vivier.eu> References: <1477644512-21716-1-git-send-email-laurent@vivier.eu> X-Provags-ID: V03:K0:1CHyhmzauPAFZPvvbOOVDpM04S3I5KORmmHhKbr0NQY/OekmKjR djZGhpPswpkfzP3V9FMgkIS/5TNq0N4Lx/T2U046G/mX/zCAIiDkDHm7+M1X63gZA3psAeB +VXP9LoxqHgFfi8TIxSl+rae1jlXAG+w12Kj06pDsHC/EBwo8FQJAa82FCcTk+zBrqRSt0l 0IId0Wu1j2TizIr1KTFNw== X-UI-Out-Filterresults: notjunk:1; V01:K0:eR+pS8EOG80=:FM3/c7S8qZsy6HYMzLg3rV pfmG+mX8XnVLKXI5eWJmoetElng33dmWce7SAyv2fpOafhYbdfRSf0uxChmv5uPzwviR5qz5P 0BcieyM42M8Yl+IWmkVd00kenuxhzzoYhG3J+IuiPAsKeZWt2xuLw2tBpBijsjhdQahjI+QHP ZFzkU/N6T6GX6H11X6XmnWkATNktLTWLgF3atYMKC4H1HB9dBgWsAUaCcP/bA6hBREKKbXS4S bsQzq8iarT6PMkM3LBGjYdOvbHd5JKgkF33kJRuTGifSKRVoY1/Liu4NfSHg/NbuqNTZECuJn fOE4CbGZ350XkJ/bVgqKCUuz+AWiOvCvyV/uOeIcYEgosT02QMhFl+XypXEi/MefUORknO526 poDWALWz5C0MeTWF6ArLhawFsxuP3jZCzckg5vRbsXtaveERo+KnXl5sUO8IyB8P/3gt2DbNp mp5aWua6/0wy0YUAEFfy0axwXx5S7dao7NP/kJ3pDR166a8QEdDgD14ZvWZokYEz4UQwc3YPT 2BPkj2J4n6rdBZtzytXFKppBvYjYWJwfD76paukI640XmJK3Cw4O++uWHA1QoPn5PjymuSiB3 nzlO/W1kEn+fXhMFDzS4uS4Ayp3w/GLOkwctky2FKkqIC1iiOW5KAtcOytX+PHFQ6dCPy70Ag PLZ5ybPKTD/4FUoisS06xqg9mXVzL6d0CIYyOl6zdIFKNAikzID0ruflGgcKJtw6OsG8= X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 212.227.126.130 Subject: [Qemu-devel] [PULL 04/18] target-m68k: add addressing modes to scc X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Laurent Vivier , gerg@uclinux.org, schwab@linux-m68k.org, agraf@suse.de, Richard Henderson Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Laurent Vivier Reviewed-by: Richard Henderson --- target-m68k/translate.c | 40 ++++++++++++++++++++-------------------- 1 file changed, 20 insertions(+), 20 deletions(-) diff --git a/target-m68k/translate.c b/target-m68k/translate.c index b407623..e595673 100644 --- a/target-m68k/translate.c +++ b/target-m68k/translate.c @@ -1008,25 +1008,6 @@ static void gen_jmpcc(DisasContext *s, int cond, TCGLabel *l1) free_cond(&c); } -DISAS_INSN(scc) -{ - DisasCompare c; - int cond; - TCGv reg, tmp; - - cond = (insn >> 8) & 0xf; - gen_cc_cond(&c, s, cond); - - tmp = tcg_temp_new(); - tcg_gen_setcond_i32(c.tcond, tmp, c.v1, c.v2); - free_cond(&c); - - reg = DREG(insn, 0); - tcg_gen_neg_i32(tmp, tmp); - tcg_gen_deposit_i32(reg, reg, tmp, 0, 8); - tcg_temp_free(tmp); -} - /* Force a TB lookup after an instruction that changes the CPU state. */ static void gen_lookup_tb(DisasContext *s) { @@ -1106,6 +1087,24 @@ static void gen_jmp_tb(DisasContext *s, int n, uint32_t dest) s->is_jmp = DISAS_TB_JUMP; } +DISAS_INSN(scc) +{ + DisasCompare c; + int cond; + TCGv tmp; + + cond = (insn >> 8) & 0xf; + gen_cc_cond(&c, s, cond); + + tmp = tcg_temp_new(); + tcg_gen_setcond_i32(c.tcond, tmp, c.v1, c.v2); + free_cond(&c); + + tcg_gen_neg_i32(tmp, tmp); + DEST_EA(env, insn, OS_BYTE, tmp, NULL); + tcg_temp_free(tmp); +} + DISAS_INSN(undef_mac) { gen_exception(s, s->pc - 2, EXCP_LINEA); @@ -3136,7 +3135,8 @@ void register_m68k_insns (CPUM68KState *env) INSN(jump, 4ec0, ffc0, M68000); INSN(addsubq, 5000, f080, M68000); INSN(addsubq, 5080, f0c0, M68000); - INSN(scc, 50c0, f0f8, CF_ISA_A); + INSN(scc, 50c0, f0f8, CF_ISA_A); /* Scc.B Dx */ + INSN(scc, 50c0, f0c0, M68000); /* Scc.B */ INSN(addsubq, 5080, f1c0, CF_ISA_A); INSN(tpf, 51f8, fff8, CF_ISA_A);