From patchwork Thu Oct 27 21:43:28 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Laurent Vivier X-Patchwork-Id: 687965 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3t4gR22Whsz9syB for ; Fri, 28 Oct 2016 08:45:02 +1100 (AEDT) Received: from localhost ([::1]:44728 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bzsTs-0006AJ-9C for incoming@patchwork.ozlabs.org; Thu, 27 Oct 2016 17:45:00 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38179) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bzsSj-0005IZ-9o for qemu-devel@nongnu.org; Thu, 27 Oct 2016 17:43:50 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bzsSf-0003Pk-Bm for qemu-devel@nongnu.org; Thu, 27 Oct 2016 17:43:49 -0400 Received: from mout.kundenserver.de ([212.227.126.187]:51667) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1bzsSf-0003Ox-1H for qemu-devel@nongnu.org; Thu, 27 Oct 2016 17:43:45 -0400 Received: from Quad.localdomain ([78.238.229.36]) by mrelayeu.kundenserver.de (mreue005) with ESMTPSA (Nemesis) id 0MRhYD-1cSeh50hRp-00SuGc; Thu, 27 Oct 2016 23:43:34 +0200 From: Laurent Vivier To: qemu-devel@nongnu.org Date: Thu, 27 Oct 2016 23:43:28 +0200 Message-Id: <1477604609-2206-3-git-send-email-laurent@vivier.eu> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1477604609-2206-1-git-send-email-laurent@vivier.eu> References: <1477604609-2206-1-git-send-email-laurent@vivier.eu> X-Provags-ID: V03:K0:wQAy1IdC66sDK7v3ABU+vLaJK78yP2MtvRfPpOLnmYajWcmWlIL lSUoGcaUXs4YTqDhqfxxbhhF+NCPw8PP9ZxjB9PDaNXSM3uBmdMyUKk7a8H2FsQBu9sNSUT NwU5tDM7Lf8CJnHSIq3OyHOZUpu08zk1yb7KnywOSH7bqD1P5lBn/NN/u1bqucgi15mqXrP nzwkYJUqeR/ZUmCDuPOiQ== X-UI-Out-Filterresults: notjunk:1; V01:K0:jIaR67GD5tc=:em3tP7MKBnVtyWE2qwqCcs DboWNxUE0gqT26bV7m7g4FKhqZ8O7uM8q4EwcI+alODEy1LuvbLvUh+ys15NXib0mEm/+zowy T1x62g/njJzeZ42cQqJCNJnIGSKEhhJ7sFxf27cK6UoW/xIf6Y28qvBsOQJfzxMHGB0eVWdRr XVysiblWIPPytlFItixPnmgD8KckfeDdliFv1y/QZ3Bha/2EyE8jo9E4/rXGNW5IqwFbniJca RL6LsnlB8szV33MkbUj1S4x2C3IjADv01WotpebNY7FJEZtTN2eBCSiC6WCfxN21dHSfFPQ3d XMv4USUJTad1Zabu6WGeNEjtXcsq0jJcA2pj5HY2PtxN7+gaxVBsAXvqOpun2qqLDHjGiKccK VIdjbkODiy7ZusvJZV51q2SIr3DZlLaYE5x+nqt7C8wpkDYekhmd1DGj1Fh3h2v+04LERRNkw +ofW84F0xwZZhQgrJ1x2DGnMToFM3mo1qLxR9fTpJHhxqnjv7vMreKJCUgDJ1cPcYu8l5nEME R0JnWURinMgD8kkriho0xKf2Ynww7ue41Cj5lNqcU/+k0BJQjogM09avtJuHsrSL2o6VFaKiC m20qb7QpqQhgZ4N9+X9YeBj8TCGUQLbKXhmzA0+icmc1AIE5qgTyQFf9wJYkusUv8h/Ka3CBZ WsfI5yWXwGu8xvY8CzIq3HJnSRo3fRkhzOytVey2QWlaGqOkFRX23NWQYALEizjgI/+4= X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 212.227.126.187 Subject: [Qemu-devel] [PATCH v2 2/3] target-m68k: Inline shifts X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Laurent Vivier , gerg@uclinux.org, schwab@linux-m68k.org, agraf@suse.de, Richard Henderson Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson Original patch from Richard Henderson Fix arithmetical/logical switch Signed-off-by: Laurent Vivier --- target-m68k/helper.c | 52 --------------------------- target-m68k/helper.h | 3 -- target-m68k/translate.c | 94 +++++++++++++++++++++++++++++++++++++------------ 3 files changed, 72 insertions(+), 77 deletions(-) diff --git a/target-m68k/helper.c b/target-m68k/helper.c index 7aed9ff..f750d3d 100644 --- a/target-m68k/helper.c +++ b/target-m68k/helper.c @@ -284,58 +284,6 @@ void HELPER(set_sr)(CPUM68KState *env, uint32_t val) m68k_switch_sp(env); } -uint32_t HELPER(shl_cc)(CPUM68KState *env, uint32_t val, uint32_t shift) -{ - uint64_t result; - - shift &= 63; - result = (uint64_t)val << shift; - - env->cc_c = (result >> 32) & 1; - env->cc_n = result; - env->cc_z = result; - env->cc_v = 0; - env->cc_x = shift ? env->cc_c : env->cc_x; - - return result; -} - -uint32_t HELPER(shr_cc)(CPUM68KState *env, uint32_t val, uint32_t shift) -{ - uint64_t temp; - uint32_t result; - - shift &= 63; - temp = (uint64_t)val << 32 >> shift; - result = temp >> 32; - - env->cc_c = (temp >> 31) & 1; - env->cc_n = result; - env->cc_z = result; - env->cc_v = 0; - env->cc_x = shift ? env->cc_c : env->cc_x; - - return result; -} - -uint32_t HELPER(sar_cc)(CPUM68KState *env, uint32_t val, uint32_t shift) -{ - uint64_t temp; - uint32_t result; - - shift &= 63; - temp = (int64_t)val << 32 >> shift; - result = temp >> 32; - - env->cc_c = (temp >> 31) & 1; - env->cc_n = result; - env->cc_z = result; - env->cc_v = result ^ val; - env->cc_x = shift ? env->cc_c : env->cc_x; - - return result; -} - /* FPU helpers. */ uint32_t HELPER(f64_to_i32)(CPUM68KState *env, float64 val) { diff --git a/target-m68k/helper.h b/target-m68k/helper.h index 2697e32..aae01f9 100644 --- a/target-m68k/helper.h +++ b/target-m68k/helper.h @@ -3,9 +3,6 @@ DEF_HELPER_1(ff1, i32, i32) DEF_HELPER_FLAGS_2(sats, TCG_CALL_NO_RWG_SE, i32, i32, i32) DEF_HELPER_2(divu, void, env, i32) DEF_HELPER_2(divs, void, env, i32) -DEF_HELPER_3(shl_cc, i32, env, i32, i32) -DEF_HELPER_3(shr_cc, i32, env, i32, i32) -DEF_HELPER_3(sar_cc, i32, env, i32, i32) DEF_HELPER_2(set_sr, void, env, i32) DEF_HELPER_3(movec, void, env, i32, i32) diff --git a/target-m68k/translate.c b/target-m68k/translate.c index 92e67eb..461d756 100644 --- a/target-m68k/translate.c +++ b/target-m68k/translate.c @@ -2348,48 +2348,98 @@ DISAS_INSN(addx_mem) gen_store(s, opsize, addr_dest, QREG_CC_N); } -/* TODO: This could be implemented without helper functions. */ DISAS_INSN(shift_im) { - TCGv reg; - int tmp; - TCGv shift; + TCGv reg = DREG(insn, 0); + int count = (insn >> 9) & 7; + int logical = insn & 8; - set_cc_op(s, CC_OP_FLAGS); + if (count == 0) { + count = 8; + } - reg = DREG(insn, 0); - tmp = (insn >> 9) & 7; - if (tmp == 0) - tmp = 8; - shift = tcg_const_i32(tmp); - /* No need to flush flags becuse we know we will set C flag. */ if (insn & 0x100) { - gen_helper_shl_cc(reg, cpu_env, reg, shift); + tcg_gen_shri_i32(QREG_CC_C, reg, 31 - count); + tcg_gen_shli_i32(QREG_CC_N, reg, count); } else { - if (insn & 8) { - gen_helper_shr_cc(reg, cpu_env, reg, shift); + tcg_gen_shri_i32(QREG_CC_C, reg, count - 1); + if (logical) { + tcg_gen_shri_i32(QREG_CC_N, reg, count); } else { - gen_helper_sar_cc(reg, cpu_env, reg, shift); + tcg_gen_sari_i32(QREG_CC_N, reg, count); } } + tcg_gen_andi_i32(QREG_CC_C, QREG_CC_C, 1); + tcg_gen_mov_i32(QREG_CC_Z, QREG_CC_N); + tcg_gen_mov_i32(QREG_CC_X, QREG_CC_C); + + /* Note that ColdFire always clears V, while M68000 sets it for + a change in the sign bit. */ + if (!logical && m68k_feature(s->env, M68K_FEATURE_M68000)) { + tcg_gen_xor_i32(QREG_CC_V, QREG_CC_N, reg); + } else { + tcg_gen_movi_i32(QREG_CC_V, 0); + } + + tcg_gen_mov_i32(reg, QREG_CC_N); + set_cc_op(s, CC_OP_FLAGS); } DISAS_INSN(shift_reg) { - TCGv reg; - TCGv shift; + TCGv reg, s32; + TCGv_i64 t64, s64; + int logical = insn & 8; reg = DREG(insn, 0); - shift = DREG(insn, 9); + t64 = tcg_temp_new_i64(); + s64 = tcg_temp_new_i64(); + s32 = tcg_temp_new(); + + /* Note that m68k truncates the shift count modulo 64, not 32. + In addition, a 64-bit shift makes it easy to find "the last + bit shifted out", for the carry flag. */ + tcg_gen_andi_i32(s32, DREG(insn, 9), 63); + tcg_gen_extu_i32_i64(s64, s32); + + /* Non-arithmetic shift clears V. Use it as a source zero here. */ + tcg_gen_movi_i32(QREG_CC_V, 0); + if (insn & 0x100) { - gen_helper_shl_cc(reg, cpu_env, reg, shift); + tcg_gen_extu_i32_i64(t64, reg); + tcg_gen_shl_i64(t64, t64, s64); + tcg_temp_free_i64(s64); + tcg_gen_extr_i64_i32(QREG_CC_N, QREG_CC_C, t64); + tcg_temp_free_i64(t64); + tcg_gen_andi_i32(QREG_CC_C, QREG_CC_C, 1); } else { - if (insn & 8) { - gen_helper_shr_cc(reg, cpu_env, reg, shift); + tcg_gen_extu_i32_i64(t64, reg); + tcg_gen_shli_i64(t64, t64, 32); + if (logical) { + tcg_gen_shr_i64(t64, t64, s64); } else { - gen_helper_sar_cc(reg, cpu_env, reg, shift); + tcg_gen_sar_i64(t64, t64, s64); } + tcg_temp_free_i64(s64); + tcg_gen_extr_i64_i32(QREG_CC_C, QREG_CC_N, t64); + tcg_temp_free_i64(t64); + tcg_gen_shri_i32(QREG_CC_C, QREG_CC_C, 31); } + tcg_gen_mov_i32(QREG_CC_Z, QREG_CC_N); + + /* Note that X = C, but only if the shift count was non-zero. */ + tcg_gen_movcond_i32(TCG_COND_NE, QREG_CC_X, s32, QREG_CC_V, + QREG_CC_C, QREG_CC_X); + tcg_temp_free(s32); + + /* Note that ColdFire always clears V (which we have done above), + while M68000 sets it for a change in the sign bit. */ + if (!logical && m68k_feature(s->env, M68K_FEATURE_M68000)) { + tcg_gen_xor_i32(QREG_CC_V, QREG_CC_N, reg); + } + + /* Write back the result. */ + tcg_gen_mov_i32(reg, QREG_CC_N); set_cc_op(s, CC_OP_FLAGS); }