From patchwork Thu Oct 27 19:09:54 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Laurent Vivier X-Patchwork-Id: 687912 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3t4cBH4SStz9s65 for ; Fri, 28 Oct 2016 06:18:47 +1100 (AEDT) Received: from localhost ([::1]:44077 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bzqCL-0001Yx-CB for incoming@patchwork.ozlabs.org; Thu, 27 Oct 2016 15:18:45 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:54842) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bzq4F-0002ma-7z for qemu-devel@nongnu.org; Thu, 27 Oct 2016 15:10:28 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bzq49-0001Kk-QU for qemu-devel@nongnu.org; Thu, 27 Oct 2016 15:10:23 -0400 Received: from mout.kundenserver.de ([217.72.192.74]:64455) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1bzq49-0001Jt-Eh for qemu-devel@nongnu.org; Thu, 27 Oct 2016 15:10:17 -0400 Received: from Quad.localdomain ([78.238.229.36]) by mrelayeu.kundenserver.de (mreue101) with ESMTPSA (Nemesis) id 0MYekE-1cLEqJ3kJu-00VPWl; Thu, 27 Oct 2016 21:10:02 +0200 From: Laurent Vivier To: qemu-devel@nongnu.org Date: Thu, 27 Oct 2016 21:09:54 +0200 Message-Id: <1477595394-23807-4-git-send-email-laurent@vivier.eu> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1477595394-23807-1-git-send-email-laurent@vivier.eu> References: <1477595394-23807-1-git-send-email-laurent@vivier.eu> X-Provags-ID: V03:K0:S+Enu4DP4TalglqFzW2QuBX5Q0ab+6X16ds2RNM8LqJT3p7RC6r XVSqxoFsQIM9pKTFHxABKbaEL3OJOYNgEbwz72wgnKMgiBpfWAZ1TdqF5MytaWR+K6+/M+O zPzicvhIPScEitE06FwWSFQKYADHiJgYFndJABNMKj54u4ljZY5r+KhHB96WlSiwgXVnWHI XfWZiIyz4x4mMXWxCPfRA== X-UI-Out-Filterresults: notjunk:1; V01:K0:kh0vmdbcDEY=:07SOSETpHn12ZLuolJcyo3 qXDQKZ2jZbHFbVQLUQuJluQ7MAEN7YVhe+9JWoDtR6FwwEvtSyNlbXNYNn96km/4CY9EjxBk+ Ghfx106ULvshdq5wxNY2xOHi0Y0sUftdAm1AT9dZ+xcRT4+v4/JMCqzfdsAJTAflfk6AfPYSd 624PXsVUT3MREgXevy3iWADyCtfBbDvdanV0g0KlhtpN08MqjLbUd/6R6u9Mw+66bI8zpFijw wUzgjYqTjl+WMGxDCEK0CwzO5iIKKH/RzRBYKJFxOq5PqxExbdq0a6lchQ8ZzWBT1ExdfBfa9 Qap58MZzpaqw0FFzebgN6XGIkRA604XvU76S2XAq9QcDr8g1Jxvq7cdV46rBIcKWNJhLuH/Qr IWUJ18aijgBtv+o9/MZnMBvdBxMgLEA3HmN9njxP8TBcFzJs0t5N8f4j7jd6j0QrQGBQqhkc5 f1NVNuGKeIATUsrYnpoUqtUy2bJZ16HxqwfohmZlmoayRDe4Ko969YukmxWLjyR7lCnLNIxdr fkLaForZaEaJqCq0ms4bVWuM7LBFNRJNyNy3gq2CDFFTZSgaw8gKSey6JvuHNrcB8MfA2pxnd 1gZoE1WjKLz/37wsTs8B7BLZMPtD6wXaasBVv/2f6NdsFEodSCLV66xaGNvn0he6vLPo973sF 982o86GJE5wli2ewFlV8D/w+GOBCg+DnsTTFGOdeklg7TJmI+5eLDqOAhqPRdr0v2xRU= X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 217.72.192.74 Subject: [Qemu-devel] [PATCH 3/3] target-m68k: shift ops manage word and byte operands X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Laurent Vivier , gerg@uclinux.org, schwab@linux-m68k.org, agraf@suse.de, Richard Henderson Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Laurent Vivier --- target-m68k/translate.c | 195 ++++++++++++++++++++++++++++++++++++++++-------- 1 file changed, 163 insertions(+), 32 deletions(-) diff --git a/target-m68k/translate.c b/target-m68k/translate.c index 13ef117..d8cf4e0 100644 --- a/target-m68k/translate.c +++ b/target-m68k/translate.c @@ -562,7 +562,7 @@ static void gen_flush_flags(DisasContext *s) s->cc_op_synced = 1; } -static TCGv gen_extend(TCGv val, int opsize, int sign) +static inline TCGv gen_extend(TCGv val, int opsize, int sign) { TCGv tmp; @@ -2348,19 +2348,43 @@ DISAS_INSN(addx_mem) gen_store(s, opsize, addr_dest, QREG_CC_N); } -DISAS_INSN(shift_im) +static inline void shift_im(DisasContext *s, uint16_t insn, int opsize) { - TCGv reg = DREG(insn, 0); int count = (insn >> 9) & 7; int logical = insn & 8; + int left = insn & 0x100; + int bits = opsize_bytes(opsize) * 8; + TCGv reg = gen_extend(DREG(insn, 0), opsize, !logical); + TCGv zero; if (count == 0) { count = 8; } - if (insn & 0x100) { - tcg_gen_shri_i32(QREG_CC_C, reg, 31 - count); + zero = tcg_const_i32(0); + if (left) { + tcg_gen_shri_i32(QREG_CC_C, reg, bits - count); tcg_gen_shli_i32(QREG_CC_N, reg, count); + + /* Note that ColdFire always clears V, + while M68000 sets if the most significant bit is changed at + any time during the shift operation */ + tcg_gen_mov_i32(QREG_CC_V, zero); + if (!logical && m68k_feature(s->env, M68K_FEATURE_M68000)) { + /* if shift count >= bits, V is (reg != 0) */ + if (count >= bits) { + tcg_gen_setcond_i32(TCG_COND_NE, QREG_CC_V, reg, zero); + } else { + TCGv t0 = tcg_temp_new(); + TCGv t1 = tcg_temp_new(); + /* mask of sign bit */ + tcg_gen_sari_i32(t0, reg, 31); + tcg_gen_shri_i32(t0, t0, bits - count); + tcg_gen_shri_i32(t1, reg, bits - count); + tcg_gen_setcond_i32(TCG_COND_NE, QREG_CC_V, t0, t1); + } + tcg_gen_neg_i32(QREG_CC_V, QREG_CC_V); + } } else { tcg_gen_shri_i32(QREG_CC_C, reg, count - 1); if (logical) { @@ -2368,30 +2392,28 @@ DISAS_INSN(shift_im) } else { tcg_gen_sari_i32(QREG_CC_N, reg, count); } + tcg_gen_mov_i32(QREG_CC_V, zero); } + + gen_ext(QREG_CC_N, QREG_CC_N, opsize, 1); tcg_gen_andi_i32(QREG_CC_C, QREG_CC_C, 1); tcg_gen_mov_i32(QREG_CC_Z, QREG_CC_N); tcg_gen_mov_i32(QREG_CC_X, QREG_CC_C); - /* Note that ColdFire always clears V, while M68000 sets it for - a change in the sign bit. */ - if (!logical && m68k_feature(s->env, M68K_FEATURE_M68000)) { - tcg_gen_xor_i32(QREG_CC_V, QREG_CC_N, reg); - } else { - tcg_gen_movi_i32(QREG_CC_V, 0); - } - - tcg_gen_mov_i32(reg, QREG_CC_N); + gen_partset_reg(opsize, DREG(insn, 0), QREG_CC_N); set_cc_op(s, CC_OP_FLAGS); } -DISAS_INSN(shift_reg) +static inline void shift_reg(DisasContext *s, uint16_t insn, int opsize) { - TCGv reg, s32; - TCGv_i64 t64, s64; int logical = insn & 8; + int left = insn & 0x100; + int bits = opsize_bytes(opsize) * 8; + TCGv reg = gen_extend(DREG(insn, 0), opsize, !logical); + TCGv s32; + TCGv_i64 t64, s64; + TCGv zero; - reg = DREG(insn, 0); t64 = tcg_temp_new_i64(); s64 = tcg_temp_new_i64(); s32 = tcg_temp_new(); @@ -2402,44 +2424,146 @@ DISAS_INSN(shift_reg) tcg_gen_andi_i32(s32, DREG(insn, 9), 63); tcg_gen_extu_i32_i64(s64, s32); - /* Non-arithmetic shift clears V. Use it as a source zero here. */ - tcg_gen_movi_i32(QREG_CC_V, 0); + zero = tcg_const_i32(0); - if (insn & 0x100) { - tcg_gen_extu_i32_i64(t64, reg); + tcg_gen_extu_i32_i64(t64, reg); + if (left) { + tcg_gen_shli_i64(t64, t64, 32 - bits); tcg_gen_shl_i64(t64, t64, s64); tcg_temp_free_i64(s64); tcg_gen_extr_i64_i32(QREG_CC_N, QREG_CC_C, t64); tcg_temp_free_i64(t64); + tcg_gen_sari_i32(QREG_CC_N, QREG_CC_N, 32 - bits); tcg_gen_andi_i32(QREG_CC_C, QREG_CC_C, 1); + + /* Note that ColdFire always clears V, + while M68000 sets if the most significant bit is changed at + any time during the shift operation */ + tcg_gen_mov_i32(QREG_CC_V, zero); + if (!logical && m68k_feature(s->env, M68K_FEATURE_M68000)) { + TCGv t0 = tcg_temp_new(); + TCGv t1 = tcg_temp_new(); + TCGv t2 = tcg_const_i32(bits); + + tcg_gen_sub_i32(t2, t2, s32); /* t2 = bits - count */ + + tcg_gen_sari_i32(t0, reg, 31); + tcg_gen_shr_i32(t0, t0, t2); + tcg_gen_shr_i32(t1, reg, t2); + tcg_temp_free(t2); + tcg_gen_setcond_i32(TCG_COND_NE, QREG_CC_V, t0, t1); + tcg_temp_free(t1); + + /* if shift count >= bits, V is (reg != 0) */ + tcg_gen_setcond_i32(TCG_COND_NE, t0, reg, zero); + tcg_gen_movcond_i32(TCG_COND_GE, QREG_CC_V, s32, t2, t0, QREG_CC_V); + + tcg_temp_free(t0); + + tcg_gen_neg_i32(QREG_CC_V, QREG_CC_V); + + /* if shift count is zero, V is 0 */ + tcg_gen_movcond_i32(TCG_COND_NE, QREG_CC_V, s32, zero, + QREG_CC_V, zero); + } } else { - tcg_gen_extu_i32_i64(t64, reg); - tcg_gen_shli_i64(t64, t64, 32); + tcg_gen_shli_i64(t64, t64, 64 - bits); if (logical) { + tcg_gen_shri_i64(t64, t64, 32 - bits); tcg_gen_shr_i64(t64, t64, s64); } else { + tcg_gen_sari_i64(t64, t64, 32 - bits); tcg_gen_sar_i64(t64, t64, s64); } tcg_temp_free_i64(s64); tcg_gen_extr_i64_i32(QREG_CC_C, QREG_CC_N, t64); tcg_temp_free_i64(t64); + gen_ext(QREG_CC_N, QREG_CC_N, opsize, 1); tcg_gen_shri_i32(QREG_CC_C, QREG_CC_C, 31); + tcg_gen_mov_i32(QREG_CC_V, zero); } tcg_gen_mov_i32(QREG_CC_Z, QREG_CC_N); - /* Note that X = C, but only if the shift count was non-zero. */ - tcg_gen_movcond_i32(TCG_COND_NE, QREG_CC_X, s32, QREG_CC_V, + /* C is cleared if shift count was zero */ + tcg_gen_movcond_i32(TCG_COND_NE, QREG_CC_C, s32, zero, + QREG_CC_C, zero); + + /* X = C, but only if the shift count was non-zero. */ + tcg_gen_movcond_i32(TCG_COND_NE, QREG_CC_X, s32, zero, QREG_CC_C, QREG_CC_X); + tcg_temp_free(zero); tcg_temp_free(s32); - /* Note that ColdFire always clears V (which we have done above), - while M68000 sets it for a change in the sign bit. */ - if (!logical && m68k_feature(s->env, M68K_FEATURE_M68000)) { - tcg_gen_xor_i32(QREG_CC_V, QREG_CC_N, reg); + /* Write back the result. */ + gen_partset_reg(opsize, DREG(insn, 0), QREG_CC_N); + set_cc_op(s, CC_OP_FLAGS); +} + +DISAS_INSN(shift8_im) +{ + shift_im(s, insn, OS_BYTE); +} + +DISAS_INSN(shift16_im) +{ + shift_im(s, insn, OS_WORD); +} + +DISAS_INSN(shift_im) +{ + shift_im(s, insn, OS_LONG); +} + +DISAS_INSN(shift8_reg) +{ + shift_reg(s, insn, OS_BYTE); +} + +DISAS_INSN(shift16_reg) +{ + shift_reg(s, insn, OS_WORD); +} + +DISAS_INSN(shift_reg) +{ + shift_reg(s, insn, OS_LONG); +} + +DISAS_INSN(shift_mem) +{ + int logical = insn & 8; + int left = insn & 0x100; + TCGv src; + TCGv addr; + + SRC_EA(env, src, OS_WORD, !logical, &addr); + tcg_gen_movi_i32(QREG_CC_V, 0); + if (left) { + tcg_gen_shri_i32(QREG_CC_C, src, 15); + tcg_gen_shli_i32(QREG_CC_N, src, 1); + + /* Note that ColdFire always clears V, + while M68000 sets if the most significant bit is changed at + any time during the shift operation */ + if (!logical && m68k_feature(s->env, M68K_FEATURE_M68000)) { + src = gen_extend(src, OS_WORD, 1); + tcg_gen_xor_i32(QREG_CC_V, QREG_CC_N, src); + } + } else { + tcg_gen_mov_i32(QREG_CC_C, src); + if (logical) { + tcg_gen_shri_i32(QREG_CC_N, src, 1); + } else { + tcg_gen_sari_i32(QREG_CC_N, src, 1); + } } - /* Write back the result. */ - tcg_gen_mov_i32(reg, QREG_CC_N); + gen_ext(QREG_CC_N, QREG_CC_N, OS_WORD, 1); + tcg_gen_andi_i32(QREG_CC_C, QREG_CC_C, 1); + tcg_gen_mov_i32(QREG_CC_Z, QREG_CC_N); + tcg_gen_mov_i32(QREG_CC_X, QREG_CC_C); + + DEST_EA(env, insn, OS_WORD, QREG_CC_N, &addr); set_cc_op(s, CC_OP_FLAGS); } @@ -3508,6 +3632,13 @@ void register_m68k_insns (CPUM68KState *env) INSN(adda, d0c0, f0c0, M68000); INSN(shift_im, e080, f0f0, CF_ISA_A); INSN(shift_reg, e0a0, f0f0, CF_ISA_A); + INSN(shift8_im, e000, f0f0, M68000); + INSN(shift16_im, e040, f0f0, M68000); + INSN(shift_im, e080, f0f0, M68000); + INSN(shift8_reg, e020, f0f0, M68000); + INSN(shift16_reg, e060, f0f0, M68000); + INSN(shift_reg, e0a0, f0f0, M68000); + INSN(shift_mem, e0c0, fcc0, M68000); INSN(undef_fpu, f000, f000, CF_ISA_A); INSN(fpu, f200, ffc0, CF_FPU); INSN(fbcc, f280, ffc0, CF_FPU);