From patchwork Thu Oct 27 00:42:27 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Laurent Vivier X-Patchwork-Id: 687421 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3t47sl33WTz9t2b for ; Thu, 27 Oct 2016 12:02:51 +1100 (AEDT) Received: from localhost ([::1]:38319 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bzZ5k-0007q0-II for incoming@patchwork.ozlabs.org; Wed, 26 Oct 2016 21:02:48 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:57372) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bzYmj-0001My-OA for qemu-devel@nongnu.org; Wed, 26 Oct 2016 20:43:10 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bzYmg-00012Z-Ke for qemu-devel@nongnu.org; Wed, 26 Oct 2016 20:43:09 -0400 Received: from mout.kundenserver.de ([212.227.126.135]:65201) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1bzYmg-00011t-BK for qemu-devel@nongnu.org; Wed, 26 Oct 2016 20:43:06 -0400 Received: from Quad.localdomain ([78.238.229.36]) by mrelayeu.kundenserver.de (mreue005) with ESMTPSA (Nemesis) id 0M7Wjr-1cnPkK0RMN-00xH9L; Thu, 27 Oct 2016 02:42:43 +0200 From: Laurent Vivier To: qemu-devel@nongnu.org Date: Thu, 27 Oct 2016 02:42:27 +0200 Message-Id: <1477528950-8115-15-git-send-email-laurent@vivier.eu> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1477528950-8115-1-git-send-email-laurent@vivier.eu> References: <1477528950-8115-1-git-send-email-laurent@vivier.eu> X-Provags-ID: V03:K0:cGbQTHo5DTUZgHg8ebP8JXRR1yRnTH4a7UXvERd7U1nkzRhgvgB tK5YnBIaDbU0juusrmhBDxiK7kl6k0M4XsvDCIXWedsGjOonAuemCJnGtgyktne6nCItM39 O7zVOwPB3Ni6PLK8I9faf2VfT19Y4+mobN+9bTB2KW9Gt8rfq/ZvVY5WWwn+Z1IQmpNZCEc U5juBtJLfYJ7cMuBZqbQg== X-UI-Out-Filterresults: notjunk:1; V01:K0:KLvoIMnBj7U=:kIk8woXrngX+kF4jCicdnq XIWoj9Ho9YKmQZzanItaq7UikLjeYtyIYI8aOCmtbGECdYrk2oSEl/0sOhcr/Vqhpkr3utSpC qt7i8791tj/wfW4jp8vajBT0swS/RqhyzNqmlZZe49MplVQdChd3H+9trDXmf9ZzVQFlOhqJM uabefcozxiJO105Gwm89ma3Q1jfzDgfBcxvags1WRTyIxbd+aEapS4pQwABVIu852pCGqbtOK 6kTWZfzKSJrHZeskHndVRLELqPI6MhdtbktZwY+of3pqYOtfA2Ec6Pe96CR0FlOjAfsAOqwao 8YIFc+iWnPHSdxpkTJnamoPKAAixYVwm/rawb4bBQM0+XzeKzp+eItJKu0ihkEXh2FxKeunW3 SaUhGMijgwMxCykGtj98XxVoIl75qFTBg4JOI+HwyTQDj9ssrrk3DXXGeA9lXP780kNHcJTgO M6FDXRJzpAqbFPITtt83mgiJFntwrbKrsvSnhviNnGRvvk4rxUQJyKCVz2f1jUJ6Z3GOG7Efr 009ZOq95HDu34UcUxy/nSii8qiC1IoeMaAChnxoqF4i2NHI/vMdTHENEFb9iVP49AkhTuw2ub ejRveFS7Kyi2l21i85wcmRONt+S3RoWepvDR6CjXGyieVmIKM68xytkk6qf4XtvPkKYFzgLuv uqU5Od5PlwOmeSub+aKrmkW9dENvg1xJzX0YmMmZ0qhTteLb9Xh3f550PmrNXbTtGbao= X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 212.227.126.135 Subject: [Qemu-devel] [PATCH v2 14/17] target-m68k: add addressing modes to neg X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Laurent Vivier , gerg@uclinux.org, schwab@linux-m68k.org, agraf@suse.de, Richard Henderson Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Laurent Vivier Reviewed-by: Richard Henderson --- target-m68k/translate.c | 20 ++++++++++++-------- 1 file changed, 12 insertions(+), 8 deletions(-) diff --git a/target-m68k/translate.c b/target-m68k/translate.c index aa09bd4..f7e6920 100644 --- a/target-m68k/translate.c +++ b/target-m68k/translate.c @@ -1631,16 +1631,20 @@ DISAS_INSN(move_from_ccr) DISAS_INSN(neg) { - TCGv reg; TCGv src1; + TCGv dest; + TCGv addr; + int opsize; - reg = DREG(insn, 0); - src1 = tcg_temp_new(); - tcg_gen_mov_i32(src1, reg); - tcg_gen_neg_i32(reg, src1); - gen_update_cc_add(reg, src1, OS_LONG); - tcg_gen_setcondi_i32(TCG_COND_NE, QREG_CC_X, src1, 0); - set_cc_op(s, CC_OP_SUBL); + opsize = insn_opsize(insn); + SRC_EA(env, src1, opsize, 1, &addr); + dest = tcg_temp_new(); + tcg_gen_neg_i32(dest, src1); + set_cc_op(s, CC_OP_SUBB + opsize); + gen_update_cc_add(dest, src1, opsize); + tcg_gen_setcondi_i32(TCG_COND_NE, QREG_CC_X, dest, 0); + DEST_EA(env, insn, opsize, dest, &addr); + tcg_temp_free(dest); } static void gen_set_sr_im(DisasContext *s, uint16_t val, int ccr_only)