From patchwork Wed Oct 26 16:36:04 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Laurent Vivier X-Patchwork-Id: 687281 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3t3xrg3gr6z9svs for ; Thu, 27 Oct 2016 04:31:15 +1100 (AEDT) Received: from localhost ([::1]:36322 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bzS2i-0006yI-HR for incoming@patchwork.ozlabs.org; Wed, 26 Oct 2016 13:31:12 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:42825) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bzRBj-0002V5-LY for qemu-devel@nongnu.org; Wed, 26 Oct 2016 12:36:28 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bzRBi-00058P-6V for qemu-devel@nongnu.org; Wed, 26 Oct 2016 12:36:27 -0400 Received: from mout.kundenserver.de ([212.227.126.134]:58746) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1bzRBh-00056S-Q8 for qemu-devel@nongnu.org; Wed, 26 Oct 2016 12:36:26 -0400 Received: from Quad.localdomain ([78.238.229.36]) by mrelayeu.kundenserver.de (mreue003) with ESMTPSA (Nemesis) id 0M371n-1crxBL2PtX-00stOO; Wed, 26 Oct 2016 18:36:20 +0200 From: Laurent Vivier To: qemu-devel@nongnu.org Date: Wed, 26 Oct 2016 18:36:04 +0200 Message-Id: <1477499766-11722-15-git-send-email-laurent@vivier.eu> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1477499766-11722-1-git-send-email-laurent@vivier.eu> References: <1477499766-11722-1-git-send-email-laurent@vivier.eu> X-Provags-ID: V03:K0:NMkpGqwYRTS1vGRacOKAcWcdfsmUzSCaEic4MPRl1UhmnHhXk5l D05451y2KvhPsLeu+fhuTtVPMkzWmCk5/iOqcxDmm82+gJ7LImLh26TxFPLMgNQPfcWBg+y F8JGRq7Qjwzdz9pTiMmJLSUOmYVmyiScaJPtmv0ow87tQfJScRcJPUV6V28LXQuPlXLfa/d Ey/vUXWdeJ3Wx3CcL3iwg== X-UI-Out-Filterresults: notjunk:1; V01:K0:JeWkdF0IKos=:840ocsA8/tRofDy5fwJ4Gt UFipvLmFHS/k2jSLo/UUOXpL7mRWcwZGvVbQgFWXmXC1smkrNOJyJn2kg7mjb2+dh2k+S3u6/ vaB9Qpw5n/RXlGzK//CTG5/bcKBrWnowY0tDGhXvK89Y5P0omfxYxrF108ZD2o2gkk5K3gDSe /5a+O1nlwXWpQzss9kEoPZ2YWvzx7/xDUd+gfyKs0TidPPlnXBbDs5ThrNe5YxrCdwHqA2SqG K+rCsdVrMCmzfxlpUVd+U9X6SB8zpGkN3cSvOWBxm56QN0r7t9wRBD0sLjXlcj+jPWGqOTlmu wqeMcm6TVn3kmhzbQJYh2YsYGr3SUEr9pgRoUub8mw2NlbYGqixaP1d5HGDFFb8t3p+GF9deQ dP+P357IUWLZN2AEZfD7Zt3ftDwZ7YrOTwCTKVzxOv7FF/pwQaBtaLKp/Qx214FGfBlzjCKDD oznQd0GXlzkL3xWs0DQyLMazzphSz9UTQIgYEt0XqNFflfP39a4Ki5E+Z1ytaUpF8sp2TdR/H OFjyWKsCo2WmZaZ6C+vD/1edC4HYDXdVjPeR8AX6ciL8QVO/bFddc1hjmEttucSl8jH5AvVP5 6O2TN9Z14T569iLFZDt8S2EAKJcG3wHmwNABrMuGeXaGlCQDMQaNLLYcfADU2uK2+nMpHuV2N 8C7dLDOgEA3pSGiUkxdhdD8pcVFTRQUboDgOQuQnmypIyXg6zWywRHKfckJFrN/qWRnQ= X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 212.227.126.134 Subject: [Qemu-devel] [PATCH 14/16] target-m68k: add/sub manage word and byte operands X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Laurent Vivier , gerg@uclinux.org, schwab@linux-m68k.org, agraf@suse.de, Richard Henderson Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Laurent Vivier Reviewed-by: Richard Henderson --- target-m68k/translate.c | 73 +++++++++++++++++++++++++++---------------------- 1 file changed, 40 insertions(+), 33 deletions(-) diff --git a/target-m68k/translate.c b/target-m68k/translate.c index 383709d..3659b9f 100644 --- a/target-m68k/translate.c +++ b/target-m68k/translate.c @@ -1253,35 +1253,37 @@ DISAS_INSN(addsub) TCGv tmp; TCGv addr; int add; + int opsize; add = (insn & 0x4000) != 0; - reg = DREG(insn, 9); + opsize = insn_opsize(insn); + reg = gen_extend(DREG(insn, 9), opsize, 1); dest = tcg_temp_new(); if (insn & 0x100) { - SRC_EA(env, tmp, OS_LONG, 0, &addr); + SRC_EA(env, tmp, opsize, 1, &addr); src = reg; } else { tmp = reg; - SRC_EA(env, src, OS_LONG, 0, NULL); + SRC_EA(env, src, opsize, 1, NULL); } if (add) { tcg_gen_add_i32(dest, tmp, src); tcg_gen_setcond_i32(TCG_COND_LTU, QREG_CC_X, dest, src); - set_cc_op(s, CC_OP_ADDL); + set_cc_op(s, CC_OP_ADDB + opsize); } else { tcg_gen_setcond_i32(TCG_COND_LTU, QREG_CC_X, tmp, src); tcg_gen_sub_i32(dest, tmp, src); - set_cc_op(s, CC_OP_SUBL); + set_cc_op(s, CC_OP_SUBB + opsize); } - gen_update_cc_add(dest, src, OS_LONG); + gen_update_cc_add(dest, src, opsize); if (insn & 0x100) { - DEST_EA(env, insn, OS_LONG, dest, &addr); + DEST_EA(env, insn, opsize, dest, &addr); } else { - tcg_gen_mov_i32(reg, dest); + gen_partset_reg(opsize, DREG(insn, 9), dest); } + tcg_temp_free(dest); } - /* Reverse the order of the bits in REG. */ DISAS_INSN(bitrev) { @@ -1889,40 +1891,48 @@ DISAS_INSN(jump) DISAS_INSN(addsubq) { - TCGv src1; - TCGv src2; + TCGv src; TCGv dest; - int val; + TCGv val; + int imm; TCGv addr; + int opsize; - SRC_EA(env, src1, OS_LONG, 0, &addr); - val = (insn >> 9) & 7; - if (val == 0) - val = 8; + if ((insn & 070) == 010) { + /* Operation on address register is always long. */ + opsize = OS_LONG; + } else { + opsize = insn_opsize(insn); + } + SRC_EA(env, src, opsize, 1, &addr); + imm = (insn >> 9) & 7; + if (imm == 0) { + imm = 8; + } + val = tcg_const_i32(imm); dest = tcg_temp_new(); - tcg_gen_mov_i32(dest, src1); + tcg_gen_mov_i32(dest, src); if ((insn & 0x38) == 0x08) { /* Don't update condition codes if the destination is an address register. */ if (insn & 0x0100) { - tcg_gen_subi_i32(dest, dest, val); + tcg_gen_sub_i32(dest, dest, val); } else { - tcg_gen_addi_i32(dest, dest, val); + tcg_gen_add_i32(dest, dest, val); } } else { - src2 = tcg_const_i32(val); if (insn & 0x0100) { - tcg_gen_setcond_i32(TCG_COND_LTU, QREG_CC_X, dest, src2); - tcg_gen_sub_i32(dest, dest, src2); - set_cc_op(s, CC_OP_SUBL); + tcg_gen_setcond_i32(TCG_COND_LTU, QREG_CC_X, dest, val); + tcg_gen_sub_i32(dest, dest, val); + set_cc_op(s, CC_OP_SUBB + opsize); } else { - tcg_gen_add_i32(dest, dest, src2); - tcg_gen_setcond_i32(TCG_COND_LTU, QREG_CC_X, dest, src2); - set_cc_op(s, CC_OP_ADDL); + tcg_gen_add_i32(dest, dest, val); + tcg_gen_setcond_i32(TCG_COND_LTU, QREG_CC_X, dest, val); + set_cc_op(s, CC_OP_ADDB + opsize); } - gen_update_cc_add(dest, src2, OS_LONG); + gen_update_cc_add(dest, val, opsize); } - DEST_EA(env, insn, OS_LONG, dest, &addr); + DEST_EA(env, insn, opsize, dest, &addr); } DISAS_INSN(tpf) @@ -3344,15 +3354,12 @@ void register_m68k_insns (CPUM68KState *env) BASE(rts, 4e75, ffff); INSN(movec, 4e7b, ffff, CF_ISA_A); BASE(jump, 4e80, ffc0); - INSN(jump, 4ec0, ffc0, CF_ISA_A); - INSN(addsubq, 5180, f1c0, CF_ISA_A); - INSN(jump, 4ec0, ffc0, M68000); + BASE(jump, 4ec0, ffc0); INSN(addsubq, 5000, f080, M68000); - INSN(addsubq, 5080, f0c0, M68000); + BASE(addsubq, 5080, f0c0); INSN(scc, 50c0, f0f8, CF_ISA_A); /* Scc.B Dx */ INSN(scc, 50c0, f0c0, M68000); /* Scc.B */ INSN(dbcc, 50c8, f0f8, M68000); - INSN(addsubq, 5080, f1c0, CF_ISA_A); INSN(tpf, 51f8, fff8, CF_ISA_A); /* Branch instructions. */