From patchwork Tue Oct 25 19:03:05 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Laurent Vivier X-Patchwork-Id: 686647 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3t3Mzn3yBNz9t0P for ; Wed, 26 Oct 2016 06:05:25 +1100 (AEDT) Received: from localhost ([::1]:57625 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bz72J-00078a-AY for incoming@patchwork.ozlabs.org; Tue, 25 Oct 2016 15:05:23 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46412) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bz70a-0005qF-Uq for qemu-devel@nongnu.org; Tue, 25 Oct 2016 15:03:37 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bz70Z-0007m2-Ek for qemu-devel@nongnu.org; Tue, 25 Oct 2016 15:03:36 -0400 Received: from mout.kundenserver.de ([217.72.192.74]:64499) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1bz70Z-0007lh-5b for qemu-devel@nongnu.org; Tue, 25 Oct 2016 15:03:35 -0400 Received: from Quad.localdomain ([78.238.229.36]) by mrelayeu.kundenserver.de (mreue101) with ESMTPSA (Nemesis) id 0MP0FD-1c1bS03tcV-006QO0; Tue, 25 Oct 2016 21:03:32 +0200 From: Laurent Vivier To: qemu-devel@nongnu.org Date: Tue, 25 Oct 2016 21:03:05 +0200 Message-Id: <1477422199-11208-10-git-send-email-laurent@vivier.eu> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1477422199-11208-1-git-send-email-laurent@vivier.eu> References: <1477422199-11208-1-git-send-email-laurent@vivier.eu> X-Provags-ID: V03:K0:UfvoFETW7QvJmghnOg263gK0j4ihJKLGK49OOsWZwhyo33SY9/7 dRx5yfslVTnzdoo/wdl6ZHqrQPeaD8Sk0kb8e95DaWIeM6u3SRYLOfxHRhfLuuYQ0HV80uW TjCcQ2Gr9LnfPq49e5VIZYkvTDnWlxk9dMMsC00nxIigPocW4QVP0BM7/I4fuozuQMlhzhu OuZ/wN2jL3en28fTCSf9w== X-UI-Out-Filterresults: notjunk:1; V01:K0:7yJD5YVVUWA=:YmjzPYI607/6OfIm1GeReN pSNBd/6CPNYvNYZZm8WO3JfU3FFXODg7VOJwyIgesKUxLsLMdBY/qxIFjzIf9a3cu2dFIpHmV EgNLIeLwigWVeErSjBuBUzZiKIBNLCWE+h2sbQUhUNe+EOae3L5v5BDVeKFmrKdWXRiu4p8s1 mMmqnpb/Sf6NxtlsQzzKND6y3+nJI1KIkrZ/e2wNiC0KAJOAcJRCUOU8Xz+QAosSlDXZnCFMw WCAkoUlttIKmzYqvcbQrvEuu+84NrD9U04HHKIme44QUybQtYGHhDSEkgwYzo6cbABiQiUhPc +IiQr8hko4RUg6yOO4HJFBsxMtfSg1jjm+Qaoa0nloVXiAY+Bzg2cgLfrqgFvm9YSGCqdxGzE R2HAuZ7MDhuA/Iq1EK9/sWVSWpiqpnBUfRF6/Vx8BpQ/EGSljKWBwysuR5/vqwBSXStk4F5BN DtP2EH2Czj52G/DdvU+KdsRURH4M43r6rAW8zi/xwlzU5OwFUuF4/6SgFcj3b8UNAVDTMDmS8 zfg2KWcsTRVkfbOJsD5ePYPqpz0p6sLodS1jFXsqCz0rEFQmjDGnjr3WDUl4RkphjgxGwvQUG eFs+FnEKWWaV+CSK9DshPhCOReIGrDWw9aGaeY7klYqHZKdA8nwjW3QqgsYfTVu9YKKPv2IZ3 JZyZaSJgHsdkG7E7MUgyxS4g3bzFQbj3iHgVb53NHoFIN/VF2nbsNed763c+C6VP3Whc= X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 217.72.192.74 Subject: [Qemu-devel] [PULL 09/23] target-m68k: REG() macro cleanup X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Laurent Vivier , gerg@uclinux.org, schwab@linux-m68k.org, agraf@suse.de, Richard Henderson Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Laurent Vivier Reviewed-by: Richard Henderson --- target-m68k/translate.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/target-m68k/translate.c b/target-m68k/translate.c index 639db76..50c55a4 100644 --- a/target-m68k/translate.c +++ b/target-m68k/translate.c @@ -59,9 +59,10 @@ static TCGv cpu_aregs[8]; static TCGv_i64 cpu_fregs[8]; static TCGv_i64 cpu_macc[4]; -#define DREG(insn, pos) cpu_dregs[((insn) >> (pos)) & 7] -#define AREG(insn, pos) cpu_aregs[((insn) >> (pos)) & 7] -#define FREG(insn, pos) cpu_fregs[((insn) >> (pos)) & 7] +#define REG(insn, pos) (((insn) >> (pos)) & 7) +#define DREG(insn, pos) cpu_dregs[REG(insn, pos)] +#define AREG(insn, pos) cpu_aregs[REG(insn, pos)] +#define FREG(insn, pos) cpu_fregs[REG(insn, pos)] #define MACREG(acc) cpu_macc[acc] #define QREG_SP cpu_aregs[7]