From patchwork Thu Oct 13 16:24:47 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Laurent Vivier X-Patchwork-Id: 681858 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3svx9r1Kqkz9rxl for ; Fri, 14 Oct 2016 03:33:20 +1100 (AEDT) Received: from localhost ([::1]:41774 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1buiwX-0002QU-4t for incoming@patchwork.ozlabs.org; Thu, 13 Oct 2016 12:33:17 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:42265) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1buip4-0004Ay-2w for qemu-devel@nongnu.org; Thu, 13 Oct 2016 12:25:35 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1buioz-0007wA-H3 for qemu-devel@nongnu.org; Thu, 13 Oct 2016 12:25:33 -0400 Received: from mx1.redhat.com ([209.132.183.28]:33706) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1buiov-0007tH-3v; Thu, 13 Oct 2016 12:25:25 -0400 Received: from int-mx09.intmail.prod.int.phx2.redhat.com (int-mx09.intmail.prod.int.phx2.redhat.com [10.5.11.22]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 816974E33A; Thu, 13 Oct 2016 16:25:24 +0000 (UTC) Received: from thinkpad.redhat.com (ovpn-112-33.ams2.redhat.com [10.36.112.33]) by int-mx09.intmail.prod.int.phx2.redhat.com (8.14.4/8.14.4) with ESMTP id u9DGP2ms010294; Thu, 13 Oct 2016 12:25:21 -0400 From: Laurent Vivier To: qemu-devel@nongnu.org Date: Thu, 13 Oct 2016 18:24:47 +0200 Message-Id: <1476375902-11715-6-git-send-email-lvivier@redhat.com> In-Reply-To: <1476375902-11715-1-git-send-email-lvivier@redhat.com> References: <1476375902-11715-1-git-send-email-lvivier@redhat.com> X-Scanned-By: MIMEDefang 2.68 on 10.5.11.22 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.38]); Thu, 13 Oct 2016 16:25:24 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [PATCH v2 05/20] target-arm: move cpu_exec_realize() to realize function X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Matthew Rosato , Peter Maydell , Eduardo Habkost , Laurent Vivier , Markus Armbruster , qemu-arm@nongnu.org, Bharata B Rao , Paolo Bonzini , David Gibson Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Setting of cpu->mp_affinity is moved from arm_cpu_initfn() to arm_cpu_realizefn() as setting of cpu_index is now done in cpu_exec_realize(). I've removed the cannot_destroy_with_object_finalize_yet field as unsafe references have been moved to cpu_exec_realize(). (tested with QOM command provided by commit 4c315c27 with "arm1026-arm-cpu") CC: Peter Maydell CC: qemu-arm@nongnu.org Signed-off-by: Laurent Vivier --- target-arm/cpu.c | 39 +++++++++++++++++---------------------- 1 file changed, 17 insertions(+), 22 deletions(-) diff --git a/target-arm/cpu.c b/target-arm/cpu.c index 7e58134..54e7991 100644 --- a/target-arm/cpu.c +++ b/target-arm/cpu.c @@ -441,23 +441,12 @@ static void arm_cpu_initfn(Object *obj) CPUState *cs = CPU(obj); ARMCPU *cpu = ARM_CPU(obj); static bool inited; - uint32_t Aff1, Aff0; cs->env_ptr = &cpu->env; cpu_exec_init(cs); - cpu_exec_realize(cs, &error_abort); cpu->cp_regs = g_hash_table_new_full(g_int_hash, g_int_equal, g_free, g_free); - /* This cpu-id-to-MPIDR affinity is used only for TCG; KVM will override it. - * We don't support setting cluster ID ([16..23]) (known as Aff2 - * in later ARM ARM versions), or any of the higher affinity level fields, - * so these bits always RAZ. - */ - Aff1 = cs->cpu_index / ARM_CPUS_PER_CLUSTER; - Aff0 = cs->cpu_index % ARM_CPUS_PER_CLUSTER; - cpu->mp_affinity = (Aff1 << ARM_AFF1_SHIFT) | Aff0; - #ifndef CONFIG_USER_ONLY /* Our inbound IRQ and FIQ lines */ if (kvm_enabled()) { @@ -577,6 +566,14 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) ARMCPU *cpu = ARM_CPU(dev); ARMCPUClass *acc = ARM_CPU_GET_CLASS(dev); CPUARMState *env = &cpu->env; + Error *local_err = NULL; + uint32_t Aff1, Aff0; + + cpu_exec_realize(cs, &local_err); + if (local_err != NULL) { + error_propagate(errp, local_err); + return; + } /* Some features automatically imply others: */ if (arm_feature(env, ARM_FEATURE_V8)) { @@ -632,6 +629,15 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) set_feature(env, ARM_FEATURE_THUMB_DSP); } + /* This cpu-id-to-MPIDR affinity is used only for TCG; KVM will override it. + * We don't support setting cluster ID ([16..23]) (known as Aff2 + * in later ARM ARM versions), or any of the higher affinity level fields, + * so these bits always RAZ. + */ + Aff1 = cs->cpu_index / ARM_CPUS_PER_CLUSTER; + Aff0 = cs->cpu_index % ARM_CPUS_PER_CLUSTER; + cpu->mp_affinity = (Aff1 << ARM_AFF1_SHIFT) | Aff0; + if (cpu->reset_hivecs) { cpu->reset_sctlr |= (1 << 13); } @@ -1534,17 +1540,6 @@ static void arm_cpu_class_init(ObjectClass *oc, void *data) cc->debug_check_watchpoint = arm_debug_check_watchpoint; cc->disas_set_info = arm_disas_set_info; - - /* - * Reason: arm_cpu_initfn() calls cpu_exec_init(), which saves - * the object in cpus -> dangling pointer after final - * object_unref(). - * - * Once this is fixed, the devices that create ARM CPUs should be - * updated not to set cannot_destroy_with_object_finalize_yet, - * unless they still screw up something else. - */ - dc->cannot_destroy_with_object_finalize_yet = true; } static void cpu_register(const ARMCPUInfo *info)