From patchwork Wed Sep 28 09:48:20 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Xu X-Patchwork-Id: 676119 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3skXwb3fLhz9t1S for ; Wed, 28 Sep 2016 19:49:17 +1000 (AEST) Received: from localhost ([::1]:57302 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bpBUH-0006wP-W6 for incoming@patchwork.ozlabs.org; Wed, 28 Sep 2016 05:49:14 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60626) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bpBTe-0006eH-6E for qemu-devel@nongnu.org; Wed, 28 Sep 2016 05:48:35 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bpBTZ-0007QP-6n for qemu-devel@nongnu.org; Wed, 28 Sep 2016 05:48:33 -0400 Received: from mx1.redhat.com ([209.132.183.28]:38634) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bpBTY-0007Q9-WE for qemu-devel@nongnu.org; Wed, 28 Sep 2016 05:48:29 -0400 Received: from int-mx10.intmail.prod.int.phx2.redhat.com (int-mx10.intmail.prod.int.phx2.redhat.com [10.5.11.23]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 286013F202; Wed, 28 Sep 2016 09:48:28 +0000 (UTC) Received: from pxdev.xzpeter.org.com (dhcp-15-192.nay.redhat.com [10.66.15.192]) by int-mx10.intmail.prod.int.phx2.redhat.com (8.14.4/8.14.4) with ESMTP id u8S9mPTZ014142; Wed, 28 Sep 2016 05:48:26 -0400 From: Peter Xu To: qemu-devel@nongnu.org Date: Wed, 28 Sep 2016 17:48:20 +0800 Message-Id: <1475056100-8803-1-git-send-email-peterx@redhat.com> X-Scanned-By: MIMEDefang 2.68 on 10.5.11.23 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.30]); Wed, 28 Sep 2016 09:48:28 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [RFC PATCH] hw/misc/edu: support MSI interrupt X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: pbonzini@redhat.com, jslaby@suse.cz, peterx@redhat.com Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" So now edu device can support both line or msi interrupt, depending on how user configures it. Signed-off-by: Peter Xu --- I'd like to have edu device as the test device for future IOMMU unit test. MSI is required for that. Hope this patch won't bring more homework for university students. docs/specs/edu.txt | 6 +++++- hw/misc/edu.c | 15 +++++++++++++-- 2 files changed, 18 insertions(+), 3 deletions(-) diff --git a/docs/specs/edu.txt b/docs/specs/edu.txt index 7f81467..888409b 100644 --- a/docs/specs/edu.txt +++ b/docs/specs/edu.txt @@ -52,7 +52,7 @@ size == 8 for the rest. 0x20 (RW) : status register, bitwise OR 0x01 -- computing factorial (RO) - 0x80 -- raise interrupt 0x01 after finishing factorial computation + 0x80 -- raise interrupt after finishing factorial computation 0x24 (RO) : interrupt status register It contains values which raised the interrupt (see interrupt raise @@ -87,6 +87,10 @@ An IRQ is generated when written to the interrupt raise register. The value appears in interrupt status register when the interrupt is raised and has to be written to the interrupt acknowledge register to lower it. +The device supports both pin and MSI interrupt. By default, pin-based +interrupt is used. Even if we are with MSI interrupt, we still need to +update the acknowledge register at the end of the IRQ handler. + DMA controller -------------- One has to specify, source, destination, size, and start the transfer. One diff --git a/hw/misc/edu.c b/hw/misc/edu.c index 888ba49..5fc35a7 100644 --- a/hw/misc/edu.c +++ b/hw/misc/edu.c @@ -24,6 +24,7 @@ #include "qemu/osdep.h" #include "hw/pci/pci.h" +#include "hw/pci/msi.h" #include "qemu/timer.h" #include "qemu/main-loop.h" /* iothread mutex */ #include "qapi/visitor.h" @@ -69,11 +70,20 @@ typedef struct { uint64_t dma_mask; } EduState; +static bool edu_msi_enabled(EduState *edu) +{ + return msi_enabled(&edu->pdev); +} + static void edu_raise_irq(EduState *edu, uint32_t val) { edu->irq_status |= val; if (edu->irq_status) { - pci_set_irq(&edu->pdev, 1); + if (edu_msi_enabled(edu)) { + msi_notify(&edu->pdev, 0); + } else { + pci_set_irq(&edu->pdev, 1); + } } } @@ -81,7 +91,7 @@ static void edu_lower_irq(EduState *edu, uint32_t val) { edu->irq_status &= ~val; - if (!edu->irq_status) { + if (!edu->irq_status && !edu_msi_enabled(edu)) { pci_set_irq(&edu->pdev, 0); } } @@ -341,6 +351,7 @@ static void pci_edu_realize(PCIDevice *pdev, Error **errp) edu, QEMU_THREAD_JOINABLE); pci_config_set_interrupt_pin(pci_conf, 1); + msi_init(pdev, 0, 1, false, false, errp); memory_region_init_io(&edu->mmio, OBJECT(edu), &edu_mmio_ops, edu, "edu-mmio", 1 << 20);