From patchwork Fri Aug 12 09:41:27 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Xu X-Patchwork-Id: 658679 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3s9pJq0qFlz9sBR for ; Sat, 13 Aug 2016 01:12:11 +1000 (AEST) Received: from localhost ([::1]:52737 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bYE80-0005JV-Vk for incoming@patchwork.ozlabs.org; Fri, 12 Aug 2016 11:12:09 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:49577) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bYDSs-0003bB-5W for qemu-devel@nongnu.org; Fri, 12 Aug 2016 10:29:44 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bYDSk-0001Da-TK for qemu-devel@nongnu.org; Fri, 12 Aug 2016 10:29:37 -0400 Received: from mx1.redhat.com ([209.132.183.28]:60188) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bYDSk-0001DK-L6 for qemu-devel@nongnu.org; Fri, 12 Aug 2016 10:29:30 -0400 Received: from int-mx13.intmail.prod.int.phx2.redhat.com (int-mx13.intmail.prod.int.phx2.redhat.com [10.5.11.26]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 5EE754E32C; Fri, 12 Aug 2016 09:41:39 +0000 (UTC) Received: from pxdev.xzpeter.org.com (dhcp-14-148.nay.redhat.com [10.66.14.148]) by int-mx13.intmail.prod.int.phx2.redhat.com (8.14.4/8.14.4) with ESMTP id u7C9fV02030415; Fri, 12 Aug 2016 05:41:36 -0400 From: Peter Xu To: qemu-devel@nongnu.org Date: Fri, 12 Aug 2016 17:41:27 +0800 Message-Id: <1470994887-21409-1-git-send-email-peterx@redhat.com> X-Scanned-By: MIMEDefang 2.68 on 10.5.11.26 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.38]); Fri, 12 Aug 2016 09:41:39 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [PATCH v2] intel_iommu: add "eim" property X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: ehabkost@redhat.com, mst@redhat.com, rkrcmar@redhat.com, peterx@redhat.com, jan.kiszka@web.de, pbonzini@redhat.com, imammedo@redhat.com, davidkiarie4@gmail.com, rth@twiddle.net Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Adding one extra property for intel-iommu device to decide whether we should support EIM bit for IR. Now we are throwing high 24 bits of dest_id away directly. This will cause interrupt issues with guests that: - enabled x2apic with cluster mode - have more than 8 vcpus (so dest_id[31:8] might be nonzero) Let's make xapic the default one, and for the brave people who would like to try EIM and know the side effects, we can do it by explicitly enabling EIM using: -device intel-iommu,intremap=on,eim=on Even after we have x2apic support, it'll still be good if we can provide a way to switch xapic/x2apic from QEMU side for e.g. debugging purpose, which is an alternative for tuning guest kernel boot parameters. We can switch the default to "on" after x2apic fully supported. Signed-off-by: Peter Xu --- hw/i386/intel_iommu.c | 16 +++++++++++++++- include/hw/i386/intel_iommu.h | 1 + 2 files changed, 16 insertions(+), 1 deletion(-) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index 28c31a2..a696f71 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -2005,6 +2005,11 @@ static const MemoryRegionOps vtd_mem_ops = { static Property vtd_properties[] = { DEFINE_PROP_UINT32("version", IntelIOMMUState, version, 0), + /* + * TODO: currently EIM is disabled by default. We can enable this + * after fully support x2apic. + */ + DEFINE_PROP_BOOL("eim", IntelIOMMUState, eim_supported, false), DEFINE_PROP_END_OF_LIST(), }; @@ -2364,7 +2369,10 @@ static void vtd_init(IntelIOMMUState *s) s->ecap = VTD_ECAP_QI | VTD_ECAP_IRO; if (x86_iommu->intr_supported) { - s->ecap |= VTD_ECAP_IR | VTD_ECAP_EIM | VTD_ECAP_MHMV; + s->ecap |= VTD_ECAP_IR | VTD_ECAP_MHMV; + if (s->eim_supported) { + s->ecap |= VTD_ECAP_EIM; + } } vtd_reset_context_cache(s); @@ -2468,6 +2476,12 @@ static void vtd_realize(DeviceState *dev, Error **errp) /* Pseudo address space under root PCI bus. */ pcms->ioapic_as = vtd_host_dma_iommu(bus, s, Q35_PSEUDO_DEVFN_IOAPIC); + /* EIM bit requires IR */ + if (s->eim_supported && !x86_iommu->intr_supported) { + error_report("EIM (Extended Interrupt Mode) bit requires intremap=on"); + exit(1); + } + /* Currently Intel IOMMU IR only support "kernel-irqchip={off|split}" */ if (x86_iommu->intr_supported && kvm_irqchip_in_kernel() && !kvm_irqchip_is_split()) { diff --git a/include/hw/i386/intel_iommu.h b/include/hw/i386/intel_iommu.h index a42dbd7..b1bc768 100644 --- a/include/hw/i386/intel_iommu.h +++ b/include/hw/i386/intel_iommu.h @@ -289,6 +289,7 @@ struct IntelIOMMUState { dma_addr_t intr_root; /* Interrupt remapping table pointer */ uint32_t intr_size; /* Number of IR table entries */ bool intr_eime; /* Extended interrupt mode enabled */ + bool eim_supported; /* Whether to allow EIM bit */ }; /* Find the VTD Address space associated with the given bus pointer,