From patchwork Thu Jul 28 14:28:12 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?C=C3=A9dric_Le_Goater?= X-Patchwork-Id: 653741 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3s0Z9q3ZSpz9sD5 for ; Fri, 29 Jul 2016 00:34:07 +1000 (AEST) Received: from localhost ([::1]:53636 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bSmNx-0003MY-6M for incoming@patchwork.ozlabs.org; Thu, 28 Jul 2016 10:34:05 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38098) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bSmIu-0007QU-Ur for qemu-devel@nongnu.org; Thu, 28 Jul 2016 10:28:55 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bSmIs-0005qv-Mc for qemu-devel@nongnu.org; Thu, 28 Jul 2016 10:28:51 -0400 Received: from 2.mo7.mail-out.ovh.net ([87.98.143.68]:51173) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bSmIs-0005ql-Ax for qemu-devel@nongnu.org; Thu, 28 Jul 2016 10:28:50 -0400 Received: from player796.ha.ovh.net (b7.ovh.net [213.186.33.57]) by mo7.mail-out.ovh.net (Postfix) with ESMTP id C8AE11000CE8 for ; Thu, 28 Jul 2016 16:28:49 +0200 (CEST) Received: from hermes.ibm.com (LFbn-1-2234-107.w90-76.abo.wanadoo.fr [90.76.55.107]) (Authenticated sender: clg@kaod.org) by player796.ha.ovh.net (Postfix) with ESMTPSA id 90D1B5C006E; Thu, 28 Jul 2016 16:28:44 +0200 (CEST) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: Peter Maydell Date: Thu, 28 Jul 2016 16:28:12 +0200 Message-Id: <1469716099-8975-3-git-send-email-clg@kaod.org> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1469716099-8975-1-git-send-email-clg@kaod.org> References: <1469716099-8975-1-git-send-email-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 1630584542648765201 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrfeeltddrieejgdejjecutefuodetggdotefrodftvfcurfhrohhfihhlvgemucfqggfjnecuuegrihhlohhuthemuceftddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmd X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x (no timestamps) [generic] X-Received-From: 87.98.143.68 Subject: [Qemu-devel] [PATCH v2 2/9] palmetto-bmc: add a "silicon-rev" property at the soc level X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Andrew Jeffery , qemu-arm@nongnu.org, qemu-devel@nongnu.org, =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" The SCU controler holds the board revision number in its 0x7C register. Let's use an alias to link a "silicon-rev" property of the soc to the "silicon-rev" property of the SCU controler. The SDMC controler "silicon-rev" property is derived from the SCU one at realize time. I did not find a better way to handle this part. Links and aliases being a one-to-one relation, I could not use one of them. I might wrong though. Signed-off-by: Cédric Le Goater --- hw/arm/aspeed.c | 2 ++ hw/arm/ast2400.c | 18 +++++++++++++----- 2 files changed, 15 insertions(+), 5 deletions(-) diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c index 54e29a865d88..1ee13d578899 100644 --- a/hw/arm/aspeed.c +++ b/hw/arm/aspeed.c @@ -74,6 +74,8 @@ static void palmetto_bmc_init(MachineState *machine) &error_abort); object_property_set_int(OBJECT(&bmc->soc), 0x120CE416, "hw-strap1", &error_abort); + object_property_set_int(OBJECT(&bmc->soc), AST2400_A0_SILICON_REV, + "silicon-rev", &error_abort); object_property_set_bool(OBJECT(&bmc->soc), true, "realized", &error_abort); diff --git a/hw/arm/ast2400.c b/hw/arm/ast2400.c index 136bf6464e1d..fa535065f765 100644 --- a/hw/arm/ast2400.c +++ b/hw/arm/ast2400.c @@ -84,8 +84,8 @@ static void ast2400_init(Object *obj) object_initialize(&s->scu, sizeof(s->scu), TYPE_ASPEED_SCU); object_property_add_child(obj, "scu", OBJECT(&s->scu), NULL); qdev_set_parent_bus(DEVICE(&s->scu), sysbus_get_default()); - qdev_prop_set_uint32(DEVICE(&s->scu), "silicon-rev", - AST2400_A0_SILICON_REV); + object_property_add_alias(obj, "silicon-rev", OBJECT(&s->scu), + "silicon-rev", &error_abort); object_property_add_alias(obj, "hw-strap1", OBJECT(&s->scu), "hw-strap1", &error_abort); object_property_add_alias(obj, "hw-strap2", OBJECT(&s->scu), @@ -102,8 +102,6 @@ static void ast2400_init(Object *obj) object_initialize(&s->sdmc, sizeof(s->sdmc), TYPE_ASPEED_SDMC); object_property_add_child(obj, "sdmc", OBJECT(&s->sdmc), NULL); qdev_set_parent_bus(DEVICE(&s->sdmc), sysbus_get_default()); - qdev_prop_set_uint32(DEVICE(&s->sdmc), "silicon-rev", - AST2400_A0_SILICON_REV); } static void ast2400_realize(DeviceState *dev, Error **errp) @@ -111,6 +109,7 @@ static void ast2400_realize(DeviceState *dev, Error **errp) int i; AST2400State *s = AST2400(dev); Error *err = NULL, *local_err = NULL; + uint32_t silicon_rev; /* IO space */ memory_region_init_io(&s->iomem, NULL, &ast2400_io_ops, NULL, @@ -192,7 +191,16 @@ static void ast2400_realize(DeviceState *dev, Error **errp) sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi), 1, AST2400_SPI_FLASH_BASE); /* SDMC - SDRAM Memory Controller */ - object_property_set_bool(OBJECT(&s->sdmc), true, "realized", &err); + silicon_rev = (uint32_t) + object_property_get_int(OBJECT(&s->scu), "silicon-rev", &err); + if (err) { + error_propagate(errp, err); + return; + } + + object_property_set_int(OBJECT(&s->sdmc), silicon_rev, "silicon-rev", &err); + object_property_set_bool(OBJECT(&s->sdmc), true, "realized", &local_err); + error_propagate(&err, local_err); if (err) { error_propagate(errp, err); return;