@@ -273,6 +273,9 @@ static void aspeed_smc_reset(DeviceState *d)
memset(s->regs, 0, sizeof s->regs);
+ /* Pretend DMA is done (u-boot initialization) */
+ s->regs[R_INTR_CTRL] = INTR_CTRL_DMA_STATUS;
+
/* Unselect all slaves */
for (i = 0; i < s->num_cs; ++i) {
s->regs[s->r_ctrl0 + i] |= CTRL_CE_STOP_ACTIVE;
@@ -297,6 +300,7 @@ static uint64_t aspeed_smc_read(void *opaque, hwaddr addr, unsigned int size)
if (addr == s->r_conf ||
addr == s->r_timings ||
addr == s->r_ce_ctrl ||
+ addr == R_INTR_CTRL ||
(addr >= s->r_ctrl0 && addr < s->r_ctrl0 + s->num_cs)) {
return s->regs[addr];
} else {
U-boot does SPI timing calibration using DMA tranfers. To let the initialization continue, we fake success by setting the DMA status of the Interrupt Control Register. For the moment, DMA support is not required as it is not used in normal operation. Signed-off-by: Cédric Le Goater <clg@kaod.org> --- hw/ssi/aspeed_smc.c | 4 ++++ 1 file changed, 4 insertions(+)