From patchwork Tue Jul 5 08:19:08 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Xu X-Patchwork-Id: 644592 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3rkH5x1xQsz9sdn for ; Tue, 5 Jul 2016 18:26:13 +1000 (AEST) Received: from localhost ([::1]:53043 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bKLgI-0006Hy-TG for incoming@patchwork.ozlabs.org; Tue, 05 Jul 2016 04:26:10 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39327) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bKLb8-0006k3-7V for qemu-devel@nongnu.org; Tue, 05 Jul 2016 04:20:51 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bKLb7-0001Vh-7H for qemu-devel@nongnu.org; Tue, 05 Jul 2016 04:20:50 -0400 Received: from mx1.redhat.com ([209.132.183.28]:41859) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bKLb7-0001Vc-1h for qemu-devel@nongnu.org; Tue, 05 Jul 2016 04:20:49 -0400 Received: from int-mx09.intmail.prod.int.phx2.redhat.com (int-mx09.intmail.prod.int.phx2.redhat.com [10.5.11.22]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id AC1BD60D4; Tue, 5 Jul 2016 08:20:48 +0000 (UTC) Received: from pxdev.xzpeter.org (vpn1-4-112.pek2.redhat.com [10.72.4.112]) by int-mx09.intmail.prod.int.phx2.redhat.com (8.14.4/8.14.4) with ESMTP id u658JcZU005634; Tue, 5 Jul 2016 04:20:42 -0400 From: Peter Xu To: qemu-devel@nongnu.org Date: Tue, 5 Jul 2016 16:19:08 +0800 Message-Id: <1467706769-12505-8-git-send-email-peterx@redhat.com> In-Reply-To: <1467706769-12505-1-git-send-email-peterx@redhat.com> References: <1467706769-12505-1-git-send-email-peterx@redhat.com> X-Scanned-By: MIMEDefang 2.68 on 10.5.11.22 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.30]); Tue, 05 Jul 2016 08:20:48 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [PATCH v11 07/28] intel_iommu: allow queued invalidation for IR X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: ehabkost@redhat.com, mst@redhat.com, jasowang@redhat.com, rkrcmar@redhat.com, peterx@redhat.com, alex.williamson@redhat.com, jan.kiszka@web.de, wexu@redhat.com, pbonzini@redhat.com, marcel@redhat.com, imammedo@redhat.com, davidkiarie4@gmail.com, rth@twiddle.net Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Queued invalidation is required for IR. This patch add basic support for interrupt cache invalidate requests. Since we currently have no IR cache implemented yet, we can just skip all interrupt cache invalidation requests for now. Signed-off-by: Peter Xu --- hw/i386/intel_iommu.c | 9 +++++++++ hw/i386/intel_iommu_internal.h | 2 ++ 2 files changed, 11 insertions(+) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index 2ac79ab..8ea408d 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -1404,6 +1404,15 @@ static bool vtd_process_inv_desc(IntelIOMMUState *s) } break; + case VTD_INV_DESC_IEC: + VTD_DPRINTF(INV, "Interrupt Entry Cache Invalidation " + "not implemented yet"); + /* + * Since currently we do not cache interrupt entries, we can + * just mark this descriptor as "good" and move on. + */ + break; + default: VTD_DPRINTF(GENERAL, "error: unkonw Invalidation Descriptor type " "hi 0x%"PRIx64 " lo 0x%"PRIx64 " type %"PRIu8, diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h index e5f514c..b648e69 100644 --- a/hw/i386/intel_iommu_internal.h +++ b/hw/i386/intel_iommu_internal.h @@ -286,6 +286,8 @@ typedef struct VTDInvDesc VTDInvDesc; #define VTD_INV_DESC_TYPE 0xf #define VTD_INV_DESC_CC 0x1 /* Context-cache Invalidate Desc */ #define VTD_INV_DESC_IOTLB 0x2 +#define VTD_INV_DESC_IEC 0x4 /* Interrupt Entry Cache + Invalidate Descriptor */ #define VTD_INV_DESC_WAIT 0x5 /* Invalidation Wait Descriptor */ #define VTD_INV_DESC_NONE 0 /* Not an Invalidate Descriptor */