From patchwork Thu Jun 2 06:48:15 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jason Wang X-Patchwork-Id: 629074 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3rKzJB4Rcgz9t5Q for ; Thu, 2 Jun 2016 17:24:42 +1000 (AEST) Received: from localhost ([::1]:45785 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1b8Mzg-0008Nr-En for incoming@patchwork.ozlabs.org; Thu, 02 Jun 2016 03:24:40 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:47590) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1b8MS1-0004W9-MX for qemu-devel@nongnu.org; Thu, 02 Jun 2016 02:49:54 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1b8MRx-0005ZL-Jt for qemu-devel@nongnu.org; Thu, 02 Jun 2016 02:49:52 -0400 Received: from mx1.redhat.com ([209.132.183.28]:34797) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1b8MRx-0005ZE-EJ for qemu-devel@nongnu.org; Thu, 02 Jun 2016 02:49:49 -0400 Received: from int-mx11.intmail.prod.int.phx2.redhat.com (int-mx11.intmail.prod.int.phx2.redhat.com [10.5.11.24]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id F32477F356; Thu, 2 Jun 2016 06:49:48 +0000 (UTC) Received: from jason-ThinkPad-T450s.redhat.com (vpn1-4-234.pek2.redhat.com [10.72.4.234]) by int-mx11.intmail.prod.int.phx2.redhat.com (8.14.4/8.14.4) with ESMTP id u526mQGA005724; Thu, 2 Jun 2016 02:49:47 -0400 From: Jason Wang To: peter.maydell@linaro.org, qemu-devel@nongnu.org Date: Thu, 2 Jun 2016 14:48:15 +0800 Message-Id: <1464850102-17829-25-git-send-email-jasowang@redhat.com> In-Reply-To: <1464850102-17829-1-git-send-email-jasowang@redhat.com> References: <1464850102-17829-1-git-send-email-jasowang@redhat.com> X-Scanned-By: MIMEDefang 2.68 on 10.5.11.24 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.26]); Thu, 02 Jun 2016 06:49:49 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [PULL V4 24/31] i.MX: Fix FEC code for MDIO operation selection X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jason Wang , Jean-Christophe Dubois Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Jean-Christophe Dubois According to the FEC chapter of i.MX25 reference manual When writing the MMFR register, bit 29 and 28 select the requested operation. * 10 means read operation with valid MII mgmt frame * 11 means read operation with non compliant MII mgmt frame * 01 means write operation with valid MII mgmt frame * 00 means write operation with non compliant MII mgmt frame So while bit 28 does change beween read/write for valid MII mgmt frame, the mening is inverted for non compliant MII mgmt frame. Bit 29 on the other hand means read/write whatever the type of mgmt frame involved. So this patch change the operation selection from bit 28 to bit 29 as it is more generic. Signed-off-by: Jean-Christophe Dubois Signed-off-by: Jason Wang --- hw/net/imx_fec.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/hw/net/imx_fec.c b/hw/net/imx_fec.c index 9055ea8..fce3661 100644 --- a/hw/net/imx_fec.c +++ b/hw/net/imx_fec.c @@ -459,10 +459,10 @@ static void imx_fec_write(void *opaque, hwaddr addr, case 0x040: /* MMFR */ /* store the value */ s->mmfr = value; - if (extract32(value, 28, 1)) { - do_phy_write(s, extract32(value, 18, 9), extract32(value, 0, 16)); - } else { + if (extract32(value, 29, 1)) { s->mmfr = do_phy_read(s, extract32(value, 18, 9)); + } else { + do_phy_write(s, extract32(value, 18, 9), extract32(value, 0, 16)); } /* raise the interrupt as the PHY operation is done */ s->eir |= FEC_INT_MII;