From patchwork Fri May 20 08:20:04 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xiao Guangrong X-Patchwork-Id: 624407 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3rB1R64Jmzz9rxl for ; Fri, 20 May 2016 18:33:06 +1000 (AEST) Received: from localhost ([::1]:53750 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1b3frk-00015v-Da for incoming@patchwork.ozlabs.org; Fri, 20 May 2016 04:33:04 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:50925) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1b3fpW-0007es-Ue for qemu-devel@nongnu.org; Fri, 20 May 2016 04:30:48 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1b3fpQ-0007qd-SU for qemu-devel@nongnu.org; Fri, 20 May 2016 04:30:45 -0400 Received: from mga03.intel.com ([134.134.136.65]:32895) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1b3fpQ-0007pl-Gu for qemu-devel@nongnu.org; Fri, 20 May 2016 04:30:40 -0400 Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga103.jf.intel.com with ESMTP; 20 May 2016 01:30:39 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.26,338,1459839600"; d="scan'208";a="985173236" Received: from xiaoreal1.sh.intel.com (HELO xiaoreal1.sh.intel.com.sh.intel.com) ([10.239.48.79]) by fmsmga002.fm.intel.com with ESMTP; 20 May 2016 01:30:34 -0700 From: Xiao Guangrong To: pbonzini@redhat.com, imammedo@redhat.com Date: Fri, 20 May 2016 16:20:04 +0800 Message-Id: <1463732412-99212-8-git-send-email-guangrong.xiao@linux.intel.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1463732412-99212-1-git-send-email-guangrong.xiao@linux.intel.com> References: <1463732412-99212-1-git-send-email-guangrong.xiao@linux.intel.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 134.134.136.65 Subject: [Qemu-devel] [PATCH v2 07/15] nvdimm acpi: set HDLE properly X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Xiao Guangrong , ehabkost@redhat.com, kvm@vger.kernel.org, mst@redhat.com, gleb@kernel.org, mtosatti@redhat.com, qemu-devel@nongnu.org, stefanha@redhat.com, dan.j.williams@intel.com, rth@twiddle.net Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Now we pass HDLE to Qemu properly, use 0 for root device and use the handle for nvdimm devices Signed-off-by: Xiao Guangrong --- hw/acpi/nvdimm.c | 22 ++++++++++++---------- 1 file changed, 12 insertions(+), 10 deletions(-) diff --git a/hw/acpi/nvdimm.c b/hw/acpi/nvdimm.c index 9531340..586c02a 100644 --- a/hw/acpi/nvdimm.c +++ b/hw/acpi/nvdimm.c @@ -488,7 +488,7 @@ static void nvdimm_build_common_dsm(Aml *dev) Aml *method, *ifctx, *function, *dsm_mem, *unpatched, *result_size; uint8_t byte_list[1]; - method = aml_method(NVDIMM_COMMON_DSM, 4, AML_SERIALIZED); + method = aml_method(NVDIMM_COMMON_DSM, 5, AML_SERIALIZED); function = aml_arg(2); dsm_mem = aml_name(NVDIMM_ACPI_MEM_ADDR); @@ -514,11 +514,10 @@ static void nvdimm_build_common_dsm(Aml *dev) /* * The HDLE indicates the DSM function is issued from which device, - * it is not used at this time as no function is supported yet. - * Currently we make it always be 0 for all the devices and will set - * the appropriate value once real function is implemented. + * it reserves 0 for root device and is the handle for NVDIMM devices. + * See the comments in nvdimm_slot_to_handle(). */ - aml_append(method, aml_store(aml_int(0x0), aml_name("HDLE"))); + aml_append(method, aml_store(aml_arg(4), aml_name("HDLE"))); aml_append(method, aml_store(aml_arg(1), aml_name("REVS"))); aml_append(method, aml_store(aml_arg(2), aml_name("FUNC"))); @@ -540,13 +539,14 @@ static void nvdimm_build_common_dsm(Aml *dev) aml_append(dev, method); } -static void nvdimm_build_device_dsm(Aml *dev) +static void nvdimm_build_device_dsm(Aml *dev, uint32_t handle) { Aml *method; method = aml_method("_DSM", 4, AML_NOTSERIALIZED); - aml_append(method, aml_return(aml_call4(NVDIMM_COMMON_DSM, aml_arg(0), - aml_arg(1), aml_arg(2), aml_arg(3)))); + aml_append(method, aml_return(aml_call5(NVDIMM_COMMON_DSM, aml_arg(0), + aml_arg(1), aml_arg(2), aml_arg(3), + aml_int(handle)))); aml_append(dev, method); } @@ -571,7 +571,7 @@ static void nvdimm_build_nvdimm_devices(GSList *device_list, Aml *root_dev) */ aml_append(nvdimm_dev, aml_name_decl("_ADR", aml_int(handle))); - nvdimm_build_device_dsm(nvdimm_dev); + nvdimm_build_device_dsm(nvdimm_dev, handle); aml_append(root_dev, nvdimm_dev); } } @@ -664,7 +664,9 @@ static void nvdimm_build_ssdt(GSList *device_list, GArray *table_offsets, aml_append(dev, field); nvdimm_build_common_dsm(dev); - nvdimm_build_device_dsm(dev); + + /* 0 is reserved for root device. */ + nvdimm_build_device_dsm(dev, 0); nvdimm_build_nvdimm_devices(device_list, dev);