From patchwork Tue May 17 07:15:41 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Xu X-Patchwork-Id: 622902 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3r882P5524z9t3v for ; Tue, 17 May 2016 17:23:41 +1000 (AEST) Received: from localhost ([::1]:48852 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1b2ZLv-000177-Qf for incoming@patchwork.ozlabs.org; Tue, 17 May 2016 03:23:39 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:42275) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1b2ZFV-0002yy-1X for qemu-devel@nongnu.org; Tue, 17 May 2016 03:17:05 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1b2ZFP-0008Q8-BM for qemu-devel@nongnu.org; Tue, 17 May 2016 03:16:59 -0400 Received: from mx1.redhat.com ([209.132.183.28]:51296) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1b2ZFP-0008Px-48 for qemu-devel@nongnu.org; Tue, 17 May 2016 03:16:55 -0400 Received: from int-mx14.intmail.prod.int.phx2.redhat.com (int-mx14.intmail.prod.int.phx2.redhat.com [10.5.11.27]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id C4FD87F6B4; Tue, 17 May 2016 07:16:54 +0000 (UTC) Received: from pxdev.xzpeter.org.com (dhcp-14-147.nay.redhat.com [10.66.14.147]) by int-mx14.intmail.prod.int.phx2.redhat.com (8.14.4/8.14.4) with ESMTP id u4H7FvDv011252; Tue, 17 May 2016 03:16:51 -0400 From: Peter Xu To: qemu-devel@nongnu.org Date: Tue, 17 May 2016 15:15:41 +0800 Message-Id: <1463469353-25642-14-git-send-email-peterx@redhat.com> In-Reply-To: <1463469353-25642-1-git-send-email-peterx@redhat.com> References: <1463469353-25642-1-git-send-email-peterx@redhat.com> X-Scanned-By: MIMEDefang 2.68 on 10.5.11.27 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.25]); Tue, 17 May 2016 07:16:54 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [PATCH v7 13/25] q35: ioapic: add support for emulated IOAPIC IR X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: ehabkost@redhat.com, mst@redhat.com, jasowang@redhat.com, rkrcmar@redhat.com, peterx@redhat.com, alex.williamson@redhat.com, jan.kiszka@web.de, wexu@redhat.com, pbonzini@redhat.com, marcel@redhat.com, imammedo@redhat.com, davidkiarie4@gmail.com, rth@twiddle.net Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" This patch translates all IOAPIC interrupts into MSI ones. One pseudo ioapic address space is added to transfer the MSI message. By default, it will be system memory address space. When IR is enabled, it will be IOMMU address space. Currently, only emulated IOAPIC is supported. Idea suggested by Jan Kiszka and Rita Sinha in the following patch: https://lists.gnu.org/archive/html/qemu-devel/2016-03/msg01933.html Signed-off-by: Peter Xu --- hw/i386/pc.c | 3 +++ hw/intc/ioapic.c | 28 ++++++++++++++++++++++++---- hw/pci-host/q35.c | 4 ++++ include/hw/i386/apic-msidef.h | 1 + include/hw/i386/ioapic_internal.h | 1 + include/hw/i386/pc.h | 4 ++++ 6 files changed, 37 insertions(+), 4 deletions(-) diff --git a/hw/i386/pc.c b/hw/i386/pc.c index 99437e0..365e82f 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -1395,6 +1395,9 @@ void pc_memory_init(PCMachineState *pcms, rom_add_option(option_rom[i].name, option_rom[i].bootindex); } pcms->fw_cfg = fw_cfg; + + /* Init default IOAPIC address space */ + pcms->ioapic_as = &address_space_memory; } qemu_irq pc_allocate_cpu_irq(void) diff --git a/hw/intc/ioapic.c b/hw/intc/ioapic.c index 51f1c0f..edd50ff 100644 --- a/hw/intc/ioapic.c +++ b/hw/intc/ioapic.c @@ -28,6 +28,8 @@ #include "hw/i386/ioapic_internal.h" #include "include/hw/pci/msi.h" #include "sysemu/kvm.h" +#include "target-i386/cpu.h" +#include "hw/i386/apic-msidef.h" //#define DEBUG_IOAPIC @@ -49,13 +51,15 @@ extern int ioapic_no; static void ioapic_service(IOAPICCommonState *s) { + AddressSpace *ioapic_as = PC_MACHINE(qdev_get_machine())->ioapic_as; + uint32_t addr, data; uint8_t i; uint8_t trig_mode; uint8_t vector; uint8_t delivery_mode; uint32_t mask; uint64_t entry; - uint8_t dest; + uint16_t dest_idx; uint8_t dest_mode; for (i = 0; i < IOAPIC_NUM_PINS; i++) { @@ -66,7 +70,14 @@ static void ioapic_service(IOAPICCommonState *s) entry = s->ioredtbl[i]; if (!(entry & IOAPIC_LVT_MASKED)) { trig_mode = ((entry >> IOAPIC_LVT_TRIGGER_MODE_SHIFT) & 1); - dest = entry >> IOAPIC_LVT_DEST_SHIFT; + /* + * By default, this would be dest_id[8] + + * reserved[8]. When IR is enabled, this would be + * interrupt_index[15] + interrupt_format[1]. This + * field never means anything, but only used to + * generate corresponding MSI. + */ + dest_idx = entry >> IOAPIC_LVT_DEST_IDX_SHIFT; dest_mode = (entry >> IOAPIC_LVT_DEST_MODE_SHIFT) & 1; delivery_mode = (entry >> IOAPIC_LVT_DELIV_MODE_SHIFT) & IOAPIC_DM_MASK; @@ -96,8 +107,17 @@ static void ioapic_service(IOAPICCommonState *s) #else (void)coalesce; #endif - apic_deliver_irq(dest, dest_mode, delivery_mode, vector, - trig_mode); + /* No matter whether IR is enabled, we translate + * the IOAPIC message into a MSI one, and its + * address space will decide whether we need a + * translation. */ + addr = APIC_DEFAULT_ADDRESS | \ + (dest_idx << MSI_ADDR_DEST_IDX_SHIFT) | + (dest_mode << MSI_ADDR_DEST_MODE_SHIFT); + data = (vector << MSI_DATA_VECTOR_SHIFT) | + (trig_mode << MSI_DATA_TRIGGER_SHIFT) | + (delivery_mode << MSI_DATA_DELIVERY_MODE_SHIFT); + stl_le_phys(ioapic_as, addr, data); } } } diff --git a/hw/pci-host/q35.c b/hw/pci-host/q35.c index 6835da1..f3d47ad 100644 --- a/hw/pci-host/q35.c +++ b/hw/pci-host/q35.c @@ -435,6 +435,7 @@ static AddressSpace *q35_host_dma_iommu(PCIBus *bus, void *opaque, int devfn) static void mch_init_dmar(MCHPCIState *mch) { + PCMachineState *pcms = PC_MACHINE(qdev_get_machine()); PCIBus *pci_bus = PCI_BUS(qdev_get_parent_bus(DEVICE(mch))); mch->iommu = INTEL_IOMMU_DEVICE(qdev_create(NULL, TYPE_INTEL_IOMMU_DEVICE)); @@ -444,6 +445,9 @@ static void mch_init_dmar(MCHPCIState *mch) sysbus_mmio_map(SYS_BUS_DEVICE(mch->iommu), 0, Q35_HOST_BRIDGE_IOMMU_ADDR); pci_setup_iommu(pci_bus, q35_host_dma_iommu, mch->iommu); + /* Pseudo address space under root PCI bus. */ + pcms->ioapic_as = q35_host_dma_iommu(pci_bus, mch->iommu, + Q35_PSEUDO_DEVFN_IOAPIC); } static void mch_realize(PCIDevice *d, Error **errp) diff --git a/include/hw/i386/apic-msidef.h b/include/hw/i386/apic-msidef.h index 6e2eb71..8b4d4cc 100644 --- a/include/hw/i386/apic-msidef.h +++ b/include/hw/i386/apic-msidef.h @@ -25,6 +25,7 @@ #define MSI_ADDR_REDIRECTION_SHIFT 3 #define MSI_ADDR_DEST_ID_SHIFT 12 +#define MSI_ADDR_DEST_IDX_SHIFT 4 #define MSI_ADDR_DEST_ID_MASK 0x00ffff0 #endif /* HW_APIC_MSIDEF_H */ diff --git a/include/hw/i386/ioapic_internal.h b/include/hw/i386/ioapic_internal.h index cab9e67..31dafb3 100644 --- a/include/hw/i386/ioapic_internal.h +++ b/include/hw/i386/ioapic_internal.h @@ -31,6 +31,7 @@ #define IOAPIC_VERSION 0x11 #define IOAPIC_LVT_DEST_SHIFT 56 +#define IOAPIC_LVT_DEST_IDX_SHIFT 48 #define IOAPIC_LVT_MASKED_SHIFT 16 #define IOAPIC_LVT_TRIGGER_MODE_SHIFT 15 #define IOAPIC_LVT_REMOTE_IRR_SHIFT 14 diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h index 96f0b66..cde6934 100644 --- a/include/hw/i386/pc.h +++ b/include/hw/i386/pc.h @@ -72,6 +72,10 @@ struct PCMachineState { uint64_t numa_nodes; uint64_t *node_mem; uint64_t *node_cpu; + + /* Address space used by IOAPIC device. All IOAPIC interrupts + * will be translated to MSI messages in the address space. */ + AddressSpace *ioapic_as; }; #define PC_MACHINE_ACPI_DEVICE_PROP "acpi-device"