From patchwork Wed May 4 21:21:05 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Laurent Vivier X-Patchwork-Id: 618688 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3r0WKX2tRjz9t43 for ; Thu, 5 May 2016 07:25:20 +1000 (AEST) Received: from localhost ([::1]:50374 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ay4IF-0006gi-0v for incoming@patchwork.ozlabs.org; Wed, 04 May 2016 17:25:15 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:51308) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ay4F8-0000WD-M9 for qemu-devel@nongnu.org; Wed, 04 May 2016 17:22:09 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ay4Ew-0006Uv-RZ for qemu-devel@nongnu.org; Wed, 04 May 2016 17:21:57 -0400 Received: from mout.kundenserver.de ([212.227.17.10]:53683) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ay4Ew-0006Mw-Jh for qemu-devel@nongnu.org; Wed, 04 May 2016 17:21:50 -0400 Received: from Quad.localdomain ([78.238.229.36]) by mrelayeu.kundenserver.de (mreue104) with ESMTPSA (Nemesis) id 0LrKW4-1bf0D01rfo-013AAc; Wed, 04 May 2016 23:21:38 +0200 From: Laurent Vivier To: qemu-devel@nongnu.org Date: Wed, 4 May 2016 23:21:05 +0200 Message-Id: <1462396869-22424-9-git-send-email-laurent@vivier.eu> X-Mailer: git-send-email 2.5.5 In-Reply-To: <1462396869-22424-1-git-send-email-laurent@vivier.eu> References: <1462392752-17703-1-git-send-email-laurent@vivier.eu> <1462396869-22424-1-git-send-email-laurent@vivier.eu> X-Provags-ID: V03:K0:j6rkkUi6DLqo4I88vNRbZeSjucyuAOSvhdZt3ZQKW1utV9ba2Ed UN8P6lK5HwUQqvpo5nZ8uLrqiMng2gd4cBItbuaPJuOoPNlaOelzudr/RxtNcJSbE0Fn0r5 zSbzRN7Q4KjHKITu6j7gI2Bz29beQ7EtBzL5N26ls7OUQGhU7OyewwOC/H+23TxG/bYruFt 7bYyJzgGToi+6FrJr4VLA== X-UI-Out-Filterresults: notjunk:1; V01:K0:0RLSl4wOLkE=:+NzPrymblDMRwTHoqy+5cO 9yr+VDA1EAP494cOd3HAJQN6arUqkOdvm6D0cOrvqcivoyb+gDI/zhmwItapBlkmEErbokLm+ 7mRE8DZJ039faqEWgcXuRua+1OqSBi3sYc+2C2bKj6tx1s6AaSH5QaZ2SPMAgzNTcciJavedw cNw6nyfdSnPfEpo3GESuFxKxXBV83JTFLZXt4q6XbTnBZranxlQDafVy0IBWX4hbJQOW5Xp7e u8Rojla5pg5AAAn7eF7GKd8o6ODJKhj+t+Tqa5EYKu9xy/E1iDAdAdDmL9skx7pd4Sr/04pEg yMjiC9SZYL9VB8LoqdxsIP9u0868QqoXrSh9kyyxAd+DH/eoHPmvnX3c6gEVUugNDZ4tgpJp/ FcwCFBz+LcPkT1L0pfw8GTKv6k8zCgZSBX924KlpiA+n+ju5dfBXSG5BIGNXFn6DdgktiOxBU PQEQvfNE9R/T8yautQMdiV4wAeSNKGQ4F+WdZwuH1OrfTLyAJDwRGA4CftyprcAoNy3gw91a3 jo26+4v5gsZmozn9SDyFq9rmujkbjpk5VzdUfBbMc4Z7h3i/FC8j+Y02p2mTVwIsn1XdVuP22 G1GoJU4iV6bxfvQ7XbE4wANeN5NJzAdAMRcKykKBI6+kNyI8992P8hVyaVdC6z4om9rBJJ+uN xwjSkt4oc48ObglIWVIm70kRopKw8dIlMydcFJLicm85ATwEp8nkfnqIGfyJDIkNxc3Q= X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 212.227.17.10 Subject: [Qemu-devel] [PATCH 48/52] target-m68k: add/sub manage word and byte operands X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Laurent Vivier , gerg@uclinux.org, schwab@linux-m68k.org, agraf@suse.de, rth@twiddle.net Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Laurent Vivier Reviewed-by: Richard Henderson --- target-m68k/translate.c | 71 ++++++++++++++++++++++++++----------------------- 1 file changed, 38 insertions(+), 33 deletions(-) diff --git a/target-m68k/translate.c b/target-m68k/translate.c index bd7394f..f880a2a 100644 --- a/target-m68k/translate.c +++ b/target-m68k/translate.c @@ -1620,35 +1620,37 @@ DISAS_INSN(addsub) TCGv tmp; TCGv addr; int add; + int opsize; add = (insn & 0x4000) != 0; - reg = DREG(insn, 9); + opsize = insn_opsize(insn); + reg = gen_extend(DREG(insn, 9), opsize, 1); dest = tcg_temp_new(); if (insn & 0x100) { - SRC_EA(env, tmp, OS_LONG, 0, &addr); + SRC_EA(env, tmp, opsize, 1, &addr); src = reg; } else { tmp = reg; - SRC_EA(env, src, OS_LONG, 0, NULL); + SRC_EA(env, src, opsize, 1, NULL); } if (add) { tcg_gen_add_i32(dest, tmp, src); tcg_gen_setcond_i32(TCG_COND_LTU, QREG_CC_X, dest, src); - set_cc_op(s, CC_OP_ADD); + set_cc_op(s, CC_OP_ADDB + opsize); } else { tcg_gen_setcond_i32(TCG_COND_LTU, QREG_CC_X, tmp, src); tcg_gen_sub_i32(dest, tmp, src); - set_cc_op(s, CC_OP_SUB); + set_cc_op(s, CC_OP_SUBB + opsize); } - gen_update_cc_add(dest, src); + gen_update_cc_add(dest, src, opsize); if (insn & 0x100) { - DEST_EA(env, insn, OS_LONG, dest, &addr); + DEST_EA(env, insn, opsize, dest, &addr); } else { - tcg_gen_mov_i32(reg, dest); + gen_partset_reg(opsize, DREG(insn, 9), dest); } + tcg_temp_free(dest); } - /* Reverse the order of the bits in REG. */ DISAS_INSN(bitrev) { @@ -2482,40 +2484,46 @@ DISAS_INSN(jump) DISAS_INSN(addsubq) { - TCGv src1; - TCGv src2; + TCGv src; TCGv dest; - int val; + TCGv val; + int imm; TCGv addr; + int opsize; - SRC_EA(env, src1, OS_LONG, 0, &addr); - val = (insn >> 9) & 7; - if (val == 0) - val = 8; + if ((insn & 070) == 010) { + /* Operation on address register is always long. */ + opsize = OS_LONG; + } else + opsize = insn_opsize(insn); + SRC_EA(env, src, opsize, 1, &addr); + imm = (insn >> 9) & 7; + if (imm == 0) + imm = 8; + val = tcg_const_i32(imm); dest = tcg_temp_new(); - tcg_gen_mov_i32(dest, src1); + tcg_gen_mov_i32(dest, src); if ((insn & 0x38) == 0x08) { /* Don't update condition codes if the destination is an address register. */ if (insn & 0x0100) { - tcg_gen_subi_i32(dest, dest, val); + tcg_gen_sub_i32(dest, dest, val); } else { - tcg_gen_addi_i32(dest, dest, val); + tcg_gen_add_i32(dest, dest, val); } } else { - src2 = tcg_const_i32(val); if (insn & 0x0100) { - tcg_gen_setcond_i32(TCG_COND_LTU, QREG_CC_X, dest, src2); - tcg_gen_sub_i32(dest, dest, src2); - set_cc_op(s, CC_OP_SUB); + tcg_gen_setcond_i32(TCG_COND_LTU, QREG_CC_X, dest, val); + tcg_gen_sub_i32(dest, dest, val); + set_cc_op(s, CC_OP_SUBB + opsize); } else { - tcg_gen_add_i32(dest, dest, src2); - tcg_gen_setcond_i32(TCG_COND_LTU, QREG_CC_X, dest, src2); - set_cc_op(s, CC_OP_ADD); + tcg_gen_add_i32(dest, dest, val); + tcg_gen_setcond_i32(TCG_COND_LTU, QREG_CC_X, dest, val); + set_cc_op(s, CC_OP_ADDB + opsize); } - gen_update_cc_add(dest, src2); + gen_update_cc_add(dest, val, opsize); } - DEST_EA(env, insn, OS_LONG, dest, &addr); + DEST_EA(env, insn, opsize, dest, &addr); } DISAS_INSN(tpf) @@ -4804,16 +4812,13 @@ void register_m68k_insns (CPUM68KState *env) BASE(rts, 4e75, ffff); INSN(movec, 4e7b, ffff, CF_ISA_A); BASE(jump, 4e80, ffc0); - INSN(jump, 4ec0, ffc0, CF_ISA_A); - INSN(addsubq, 5180, f1c0, CF_ISA_A); - INSN(jump, 4ec0, ffc0, M68000); + BASE(jump, 4ec0, ffc0); INSN(addsubq, 5000, f080, M68000); - INSN(addsubq, 5080, f0c0, M68000); + BASE(addsubq, 5080, f0c0); INSN(scc, 50c0, f0f8, CF_ISA_A); INSN(scc_mem, 50c0, f0c0, M68000); INSN(scc, 50c0, f0f8, M68000); INSN(dbcc, 50c8, f0f8, M68000); - INSN(addsubq, 5080, f1c0, CF_ISA_A); INSN(tpf, 51f8, fff8, CF_ISA_A); /* Branch instructions. */