From patchwork Wed May 4 20:11:54 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Laurent Vivier X-Patchwork-Id: 618641 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3r0TyW5kFfz9t5C for ; Thu, 5 May 2016 06:23:47 +1000 (AEST) Received: from localhost ([::1]:50077 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ay3Kg-0003bK-96 for incoming@patchwork.ozlabs.org; Wed, 04 May 2016 16:23:42 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46574) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ay3Bs-0001hb-Ek for qemu-devel@nongnu.org; Wed, 04 May 2016 16:14:42 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ay3Bg-0003Xo-F2 for qemu-devel@nongnu.org; Wed, 04 May 2016 16:14:30 -0400 Received: from smtp1-g21.free.fr ([212.27.42.1]:29205) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ay3Bg-0003RC-78 for qemu-devel@nongnu.org; Wed, 04 May 2016 16:14:24 -0400 Received: from Quad.localdomain (unknown [IPv6:2a01:e34:eeee:5240:12c3:7bff:fe6b:9a76]) by smtp1-g21.free.fr (Postfix) with ESMTPS id 61D39B00345; Wed, 4 May 2016 20:07:46 +0200 (CEST) From: Laurent Vivier To: qemu-devel@nongnu.org Date: Wed, 4 May 2016 22:11:54 +0200 Message-Id: <1462392752-17703-15-git-send-email-laurent@vivier.eu> X-Mailer: git-send-email 2.5.5 In-Reply-To: <1462392752-17703-1-git-send-email-laurent@vivier.eu> References: <1462392752-17703-1-git-send-email-laurent@vivier.eu> X-detected-operating-system: by eggs.gnu.org: Windows NT kernel [generic] [fuzzy] X-Received-From: 212.27.42.1 Subject: [Qemu-devel] [PATCH 14/52] target-m68k: update move to/from ccr/sr X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Laurent Vivier , rth@twiddle.net, schwab@linux-m68k.org, agraf@suse.de, gerg@uclinux.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Laurent Vivier Reviewed-by: Richard Henderson --- target-m68k/translate.c | 53 ++++++++++++++++++++----------------------------- 1 file changed, 22 insertions(+), 31 deletions(-) diff --git a/target-m68k/translate.c b/target-m68k/translate.c index c7331dc..cddc2b5 100644 --- a/target-m68k/translate.c +++ b/target-m68k/translate.c @@ -1359,12 +1359,10 @@ static TCGv gen_get_ccr(DisasContext *s) DISAS_INSN(move_from_ccr) { - TCGv reg; TCGv ccr; ccr = gen_get_ccr(s); - reg = DREG(insn, 0); - gen_partset_reg(OS_WORD, reg, ccr); + DEST_EA(env, insn, OS_WORD, ccr, NULL); } DISAS_INSN(neg) @@ -1391,37 +1389,31 @@ static void gen_set_sr_im(DisasContext *s, uint16_t val, int ccr_only) } } -static void gen_set_sr(CPUM68KState *env, DisasContext *s, uint16_t insn, - int ccr_only) +static void gen_set_sr(DisasContext *s, TCGv val, int ccr_only) { TCGv tmp; - TCGv reg; + tmp = tcg_temp_new(); + tcg_gen_andi_i32(QREG_CC_DEST, val, 0xf); + tcg_gen_shri_i32(tmp, val, 4); + tcg_gen_andi_i32(QREG_CC_X, tmp, 1); + if (!ccr_only) { + gen_helper_set_sr(cpu_env, val); + } +} +static void gen_move_to_sr(CPUM68KState *env, DisasContext *s, uint16_t insn, + int ccr_only) +{ + TCGv src; s->cc_op = CC_OP_FLAGS; - if ((insn & 0x38) == 0) - { - tmp = tcg_temp_new(); - reg = DREG(insn, 0); - tcg_gen_andi_i32(QREG_CC_DEST, reg, 0xf); - tcg_gen_shri_i32(tmp, reg, 4); - tcg_gen_andi_i32(QREG_CC_X, tmp, 1); - if (!ccr_only) { - gen_helper_set_sr(cpu_env, reg); - } - } - else if ((insn & 0x3f) == 0x3c) - { - uint16_t val; - val = read_im16(env, s); - gen_set_sr_im(s, val, ccr_only); - } - else - disas_undef(env, s, insn); + SRC_EA(env, src, OS_WORD, 0, NULL); + gen_set_sr(s, src, ccr_only); } + DISAS_INSN(move_to_ccr) { - gen_set_sr(env, s, insn, 1); + gen_move_to_sr(env, s, insn, 1); } DISAS_INSN(not) @@ -1953,16 +1945,14 @@ DISAS_INSN(strldsr) DISAS_INSN(move_from_sr) { - TCGv reg; TCGv sr; - if (IS_USER(s)) { + if (IS_USER(s) && !m68k_feature(env, M68K_FEATURE_M68000)) { gen_exception(s, s->pc - 2, EXCP_PRIVILEGE); return; } sr = gen_get_sr(s); - reg = DREG(insn, 0); - gen_partset_reg(OS_WORD, reg, sr); + DEST_EA(env, insn, OS_WORD, sr, NULL); } DISAS_INSN(move_to_sr) @@ -1971,7 +1961,7 @@ DISAS_INSN(move_to_sr) gen_exception(s, s->pc - 2, EXCP_PRIVILEGE); return; } - gen_set_sr(env, s, insn, 0); + gen_move_to_sr(env, s, insn, 0); gen_lookup_tb(s); } @@ -2868,6 +2858,7 @@ void register_m68k_insns (CPUM68KState *env) BASE(clr, 4200, ff00); BASE(undef, 42c0, ffc0); INSN(move_from_ccr, 42c0, fff8, CF_ISA_A); + INSN(move_from_ccr, 42c0, ffc0, M68000); INSN(neg, 4480, fff8, CF_ISA_A); INSN(neg, 4400, ff00, M68000); INSN(undef, 44c0, ffc0, M68000);