From patchwork Thu Apr 28 07:05:28 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Xu X-Patchwork-Id: 616038 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3qwSc42T01z9t6g for ; Thu, 28 Apr 2016 17:08:52 +1000 (AEST) Received: from localhost ([::1]:46888 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1avg4A-00005i-6T for incoming@patchwork.ozlabs.org; Thu, 28 Apr 2016 03:08:50 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:41408) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1avg1S-0002pK-Ga for qemu-devel@nongnu.org; Thu, 28 Apr 2016 03:06:09 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1avg1R-0007Z2-Nj for qemu-devel@nongnu.org; Thu, 28 Apr 2016 03:06:02 -0400 Received: from mx1.redhat.com ([209.132.183.28]:47374) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1avg1R-0007Yw-JV for qemu-devel@nongnu.org; Thu, 28 Apr 2016 03:06:01 -0400 Received: from int-mx10.intmail.prod.int.phx2.redhat.com (int-mx10.intmail.prod.int.phx2.redhat.com [10.5.11.23]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 470266035; Thu, 28 Apr 2016 07:06:01 +0000 (UTC) Received: from pxdev.xzpeter.org.com (dhcp-14-238.nay.redhat.com [10.66.14.238]) by int-mx10.intmail.prod.int.phx2.redhat.com (8.14.4/8.14.4) with ESMTP id u3S75nNH007114; Thu, 28 Apr 2016 03:05:57 -0400 From: Peter Xu To: qemu-devel@nongnu.org Date: Thu, 28 Apr 2016 15:05:28 +0800 Message-Id: <1461827144-6937-3-git-send-email-peterx@redhat.com> In-Reply-To: <1461827144-6937-1-git-send-email-peterx@redhat.com> References: <1461827144-6937-1-git-send-email-peterx@redhat.com> X-Scanned-By: MIMEDefang 2.68 on 10.5.11.23 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.38]); Thu, 28 Apr 2016 07:06:01 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [PATCH v5 02/18] intel_iommu: allow queued invalidation for IR X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: ehabkost@redhat.com, mst@redhat.com, jasowang@redhat.com, rkrcmar@redhat.com, peterx@redhat.com, alex.williamson@redhat.com, jan.kiszka@web.de, wexu@redhat.com, pbonzini@redhat.com, marcel@redhat.com, imammedo@redhat.com, rth@twiddle.net Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Queued invalidation is required for IR. This patch add basic support for interrupt cache invalidate requests. Since we currently have no IR cache implemented yet, we can just skip all interrupt cache invalidation requests for now. Signed-off-by: Peter Xu --- hw/i386/intel_iommu.c | 9 +++++++++ hw/i386/intel_iommu_internal.h | 2 ++ 2 files changed, 11 insertions(+) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index 347718f..4b0558e 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -1400,6 +1400,15 @@ static bool vtd_process_inv_desc(IntelIOMMUState *s) } break; + case VTD_INV_DESC_IEC: + VTD_DPRINTF(INV, "Interrupt Entry Cache Invalidation " + "not implemented yet"); + /* + * Since currently we do not cache interrupt entries, we can + * just mark this descriptor as "good" and move on. + */ + break; + default: VTD_DPRINTF(GENERAL, "error: unkonw Invalidation Descriptor type " "hi 0x%"PRIx64 " lo 0x%"PRIx64 " type %"PRIu8, diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h index e5f514c..b648e69 100644 --- a/hw/i386/intel_iommu_internal.h +++ b/hw/i386/intel_iommu_internal.h @@ -286,6 +286,8 @@ typedef struct VTDInvDesc VTDInvDesc; #define VTD_INV_DESC_TYPE 0xf #define VTD_INV_DESC_CC 0x1 /* Context-cache Invalidate Desc */ #define VTD_INV_DESC_IOTLB 0x2 +#define VTD_INV_DESC_IEC 0x4 /* Interrupt Entry Cache + Invalidate Descriptor */ #define VTD_INV_DESC_WAIT 0x5 /* Invalidation Wait Descriptor */ #define VTD_INV_DESC_NONE 0 /* Not an Invalidate Descriptor */